diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 52d1275..8086da2 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -24,7 +24,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -55,10 +55,10 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -136,7 +136,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -146,11 +146,6 @@ This means code written to parse this file will need to be revisited each subseq - - - - -
diff --git a/lab2CA.runs/.jobs/vrs_config_37.xml b/lab2CA.runs/.jobs/vrs_config_37.xml new file mode 100644 index 0000000..b013dc9 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_37.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/lab2CA.runs/impl_1/CPU9bits.tcl b/lab2CA.runs/impl_1/CPU9bits.tcl new file mode 100644 index 0000000..f9f06bc --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits.tcl @@ -0,0 +1,150 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + create_project -in_memory -part xc7k160tifbg484-2L + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project] + set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project] + set_property ip_output_repo C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp + link_design -top CPU9bits -part xc7k160tifbg484-2L + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force CPU9bits_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force CPU9bits_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file CPU9bits_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force CPU9bits_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force CPU9bits_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + diff --git a/lab2CA.runs/impl_1/CPU9bits.vdi b/lab2CA.runs/impl_1/CPU9bits.vdi new file mode 100644 index 0000000..f2aed17 --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits.vdi @@ -0,0 +1,450 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Wed Mar 20 10:54:16 2019 +# Process ID: 6632 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 +# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source CPU9bits.tcl -notrace +Command: link_design -top CPU9bits -part xc7k160tifbg484-2L +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Project 1-479] Netlist was created with Vivado 2018.3 +INFO: [Device 21-403] Loading part xc7k160tifbg484-2L +INFO: [Project 1-570] Preparing netlist for logic optimization +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 577.477 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 582.992 ; gain = 327.441 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.158 . Memory (MB): peak = 584.691 ; gain = 1.699 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1120.242 ; gain = 535.551 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1215.434 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1215.434 ; gain = 0.000 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.042 . Memory (MB): peak = 1215.434 ; gain = 0.000 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.044 . Memory (MB): peak = 1215.434 ; gain = 0.000 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +Phase 5 Shift Register Optimization | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1215.434 ; gain = 0.000 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.075 . Memory (MB): peak = 1215.434 ; gain = 0.000 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1215.434 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1215.434 ; gain = 0.000 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1215.434 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1215.434 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1215.434 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 67eaf6c9 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1215.434 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1215.434 ; gain = 632.441 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1215.434 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx +Command: report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1215.434 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e8bce05 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1215.434 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1215.434 ; gain = 0.000 + +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device +INFO: [Timing 38-35] Done setting XDC timing constraints. +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e57f37ca + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1228.512 ; gain = 13.078 + +Phase 1.3 Build Placer Netlist Model +Phase 1.3 Build Placer Netlist Model | Checksum: 12d43b0ad + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1228.512 ; gain = 13.078 + +Phase 1.4 Constrain Clocks/Macros +Phase 1.4 Constrain Clocks/Macros | Checksum: 12d43b0ad + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1228.512 ; gain = 13.078 +Phase 1 Placer Initialization | Checksum: 12d43b0ad + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1228.512 ; gain = 13.078 + +Phase 2 Global Placement + +Phase 2.1 Floorplanning +Phase 2.1 Floorplanning | Checksum: 12d43b0ad + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1230.293 ; gain = 14.859 +WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer +Phase 2 Global Placement | Checksum: 1864333f5 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1238.859 ; gain = 23.426 + +Phase 3 Detail Placement + +Phase 3.1 Commit Multi Column Macros +Phase 3.1 Commit Multi Column Macros | Checksum: 1864333f5 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1238.859 ; gain = 23.426 + +Phase 3.2 Commit Most Macros & LUTRAMs +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b035ff86 + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1238.859 ; gain = 23.426 + +Phase 3.3 Area Swap Optimization +Phase 3.3 Area Swap Optimization | Checksum: 1a32c6abd + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1238.859 ; gain = 23.426 + +Phase 3.4 Pipeline Register Optimization +Phase 3.4 Pipeline Register Optimization | Checksum: 1a32c6abd + +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1238.859 ; gain = 23.426 + +Phase 3.5 Small Shape Detail Placement +Phase 3.5 Small Shape Detail Placement | Checksum: fab459d9 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.652 ; gain = 32.219 + +Phase 3.6 Re-assign LUT pins +Phase 3.6 Re-assign LUT pins | Checksum: fab459d9 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.652 ; gain = 32.219 + +Phase 3.7 Pipeline Register Optimization +Phase 3.7 Pipeline Register Optimization | Checksum: fab459d9 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.652 ; gain = 32.219 +Phase 3 Detail Placement | Checksum: fab459d9 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.652 ; gain = 32.219 + +Phase 4 Post Placement Optimization and Clean-Up + +Phase 4.1 Post Commit Optimization +Phase 4.1 Post Commit Optimization | Checksum: fab459d9 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.652 ; gain = 32.219 + +Phase 4.2 Post Placement Cleanup +Phase 4.2 Post Placement Cleanup | Checksum: fab459d9 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.652 ; gain = 32.219 + +Phase 4.3 Placer Reporting +Phase 4.3 Placer Reporting | Checksum: fab459d9 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.652 ; gain = 32.219 + +Phase 4.4 Final Placement Cleanup +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1247.652 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 12de424c6 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.652 ; gain = 32.219 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 12de424c6 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.652 ; gain = 32.219 +Ending Placer Task | Checksum: 1217184e4 + +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1247.652 ; gain = 32.219 +INFO: [Common 17-83] Releasing license: Implementation +37 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +place_design completed successfully +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1247.652 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 1247.652 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.049 . Memory (MB): peak = 1247.652 ; gain = 0.000 +INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb +INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1247.652 ; gain = 0.000 +Command: route_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' +Running DRC as a precondition to command route_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + + +Starting Routing Task +INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs +Checksum: PlaceDB: b70f4e2d ConstDB: 0 ShapeSum: 6a6236b7 RouteDB: 0 + +Phase 1 Build RT Design +Phase 1 Build RT Design | Checksum: ffbb244b + +Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1468.047 ; gain = 220.355 +Post Restoration Checksum: NetGraph: 5f6c3d5a NumContArr: a04ee6f1 Constraints: 0 Timing: 0 + +Phase 2 Router Initialization +INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. + +Phase 2.1 Fix Topology Constraints +Phase 2.1 Fix Topology Constraints | Checksum: ffbb244b + +Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1472.582 ; gain = 224.891 + +Phase 2.2 Pre Route Cleanup +Phase 2.2 Pre Route Cleanup | Checksum: ffbb244b + +Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1472.582 ; gain = 224.891 + Number of Nodes with overlaps = 0 +Phase 2 Router Initialization | Checksum: 7ea84813 + +Time (s): cpu = 00:00:28 ; elapsed = 00:00:21 . Memory (MB): peak = 1496.957 ; gain = 249.266 + +Phase 3 Initial Routing +Phase 3 Initial Routing | Checksum: 16fa702c6 + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.957 ; gain = 249.266 + +Phase 4 Rip-up And Reroute + +Phase 4.1 Global Iteration 0 + Number of Nodes with overlaps = 0 +Phase 4.1 Global Iteration 0 | Checksum: fb3beefb + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.957 ; gain = 249.266 +Phase 4 Rip-up And Reroute | Checksum: fb3beefb + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.957 ; gain = 249.266 + +Phase 5 Delay and Skew Optimization +Phase 5 Delay and Skew Optimization | Checksum: fb3beefb + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.957 ; gain = 249.266 + +Phase 6 Post Hold Fix + +Phase 6.1 Hold Fix Iter +Phase 6.1 Hold Fix Iter | Checksum: fb3beefb + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.957 ; gain = 249.266 +Phase 6 Post Hold Fix | Checksum: fb3beefb + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.957 ; gain = 249.266 + +Phase 7 Route finalize + +Router Utilization Summary + Global Vertical Routing Utilization = 2.61131e-05 % + Global Horizontal Routing Utilization = 0.000170503 % + Routable Net Status* + *Does not include unroutable nets such as driverless and loadless. + Run report_route_status for detailed report. + Number of Failed Nets = 0 + Number of Unrouted Nets = 0 + Number of Partially Routed Nets = 0 + Number of Node Overlaps = 0 + +Congestion Report +North Dir 1x1 Area, Max Cong = 0.900901%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 1.47059%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. + +------------------------------ +Reporting congestion hotspots +------------------------------ +Direction: North +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: South +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: East +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 +Direction: West +---------------- +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 + +Phase 7 Route finalize | Checksum: fb3beefb + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.957 ; gain = 249.266 + +Phase 8 Verifying routed nets + + Verification completed successfully +Phase 8 Verifying routed nets | Checksum: fb3beefb + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.957 ; gain = 249.266 + +Phase 9 Depositing Routes +Phase 9 Depositing Routes | Checksum: fb3beefb + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.957 ; gain = 249.266 +INFO: [Route 35-16] Router Completed Successfully + +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1496.957 ; gain = 249.266 + +Routing Is Done. +INFO: [Common 17-83] Releasing license: Implementation +49 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. +route_design completed successfully +route_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 1496.957 ; gain = 249.305 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1496.957 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +Writing placer database... +Writing XDEF routing. +Writing XDEF routing logical nets. +Writing XDEF routing special nets. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1496.957 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx +Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx +INFO: [IP_Flow 19-1839] IP Catalog is up to date. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt. +report_drc completed successfully +INFO: [runtcl-4] Executing : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx +Command: report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [DRC 23-133] Running Methodology with 2 threads +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt. +report_methodology completed successfully +INFO: [runtcl-4] Executing : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx +Command: report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx +WARNING: [Power 33-232] No user defined clocks were found in the design! +Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate +INFO: [Timing 38-35] Done setting XDC timing constraints. +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +60 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. +INFO: [runtcl-4] Executing : report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt +INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. +INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt +INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs +INFO: [Common 17-206] Exiting Vivado at Wed Mar 20 10:55:21 2019... diff --git a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb new file mode 100644 index 0000000..3390588 Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt new file mode 100644 index 0000000..628651f --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt @@ -0,0 +1,15 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:55:21 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx +| Design : CPU9bits +| Device : 7k160ti-fbg484 +| Speed File : -2L PRODUCTION 1.12 2017-02-17 +--------------------------------------------------------------------------------------------------------------------------------------------------------- + +Bus Skew Report + +No bus skew constraints + diff --git a/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt new file mode 100644 index 0000000..945407b --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt @@ -0,0 +1,154 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:55:21 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt +| Design : CPU9bits +| Device : 7k160ti-fbg484 +| Speed File : -2L PRODUCTION 1.12 2017-02-17 +| Temperature Grade : I +------------------------------------------------------------------------------------------- + +Clock Utilization Report + +Table of Contents +----------------- +1. Clock Primitive Utilization +2. Global Clock Resources +3. Global Clock Source Details +4. Clock Regions: Key Resource Utilization +5. Clock Regions : Global Clock Summary +6. Device Cell Placement Summary for Global Clock g0 +7. Clock Region Cell Placement per Global Clock: Region X0Y1 + +1. Clock Primitive Utilization +------------------------------ + ++----------+------+-----------+-----+--------------+--------+ +| Type | Used | Available | LOC | Clock Region | Pblock | ++----------+------+-----------+-----+--------------+--------+ +| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | +| BUFH | 0 | 120 | 0 | 0 | 0 | +| BUFIO | 0 | 32 | 0 | 0 | 0 | +| BUFMR | 0 | 16 | 0 | 0 | 0 | +| BUFR | 0 | 32 | 0 | 0 | 0 | +| MMCM | 0 | 8 | 0 | 0 | 0 | +| PLL | 0 | 8 | 0 | 0 | 0 | ++----------+------+-----------+-----+--------------+--------+ + + +2. Global Clock Resources +------------------------- + ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 3 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | ++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +3. Global Clock Source Details +------------------------------ + ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +| src0 | g0 | IBUF/O | None | IOB_X0Y78 | X0Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | ++-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) + + +4. Clock Regions: Key Resource Utilization +------------------------------------------ + ++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ +| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | +| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 | +| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | ++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ +* Global Clock column represents track count; while other columns represents cell counts + + +5. Clock Regions : Global Clock Summary +--------------------------------------- + +All Modules ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 1 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +6. Device Cell Placement Summary for Global Clock g0 +---------------------------------------------------- + ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +| g0 | BUFG/O | n/a | | | | 3 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ +* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources +** IO Loads column represents load cell count of IO types +*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) +**** GT Loads column represents load cell count of GT types + + ++----+----+----+ +| | X0 | X1 | ++----+----+----+ +| Y4 | 0 | 0 | +| Y3 | 0 | 0 | +| Y2 | 0 | 0 | +| Y1 | 3 | 0 | +| Y0 | 0 | 0 | ++----+----+----+ + + +7. Clock Region Cell Placement per Global Clock: Region X0Y1 +------------------------------------------------------------ + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +| g0 | n/a | BUFG/O | None | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + + +# Location of BUFG Primitives +set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] + +# Location of IO Primitives which is load of clock spine + +# Location of clock ports +set_property LOC IOB_X0Y78 [get_ports clk] + +# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" +#startgroup +create_pblock {CLKAG_clk_IBUF_BUFG} +add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] +resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} +#endgroup diff --git a/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt new file mode 100644 index 0000000..3fc76ab --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt @@ -0,0 +1,65 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:54:50 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt +| Design : CPU9bits +| Device : xc7k160ti +------------------------------------------------------------------------------------- + +Control Set Information + +Table of Contents +----------------- +1. Summary +2. Histogram +3. Flip-Flop Distribution +4. Detailed Control Set Information + +1. Summary +---------- + ++----------------------------------------------------------+-------+ +| Status | Count | ++----------------------------------------------------------+-------+ +| Number of unique control sets | 1 | +| Unused register locations in slices containing registers | 5 | ++----------------------------------------------------------+-------+ + + +2. Histogram +------------ + ++--------+--------------+ +| Fanout | Control Sets | ++--------+--------------+ +| 3 | 1 | ++--------+--------------+ + + +3. Flip-Flop Distribution +------------------------- + ++--------------+-----------------------+------------------------+-----------------+--------------+ +| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | ++--------------+-----------------------+------------------------+-----------------+--------------+ +| No | No | No | 3 | 1 | +| No | No | Yes | 0 | 0 | +| No | Yes | No | 0 | 0 | +| Yes | No | No | 0 | 0 | +| Yes | No | Yes | 0 | 0 | +| Yes | Yes | No | 0 | 0 | ++--------------+-----------------------+------------------------+-----------------+--------------+ + + +4. Detailed Control Set Information +----------------------------------- + ++----------------+---------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+---------------+------------------+------------------+----------------+ +| clk_IBUF_BUFG | | | 1 | 3 | ++----------------+---------------+------------------+------------------+----------------+ + + diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb b/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb new file mode 100644 index 0000000..0158a2a Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt b/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt new file mode 100644 index 0000000..6df0bf9 --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt @@ -0,0 +1,61 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +--------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:54:48 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx +| Design : CPU9bits +| Device : xc7k160tifbg484-2L +| Speed File : -2L +| Design State : Synthesized +--------------------------------------------------------------------------------------------------------------- + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +3 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, done, reset. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +3 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, done, reset. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb b/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb new file mode 100644 index 0000000..0158a2a Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt new file mode 100644 index 0000000..6f6622c --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt @@ -0,0 +1,61 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:55:20 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx +| Design : CPU9bits +| Device : xc7k160tifbg484-2L +| Speed File : -2L +| Design State : Fully Routed +------------------------------------------------------------------------------------------------------------------ + +Report DRC + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Ruledeck: default + Max violations: + Violations found: 3 ++----------+------------------+-----------------------------------------------------+------------+ +| Rule | Severity | Description | Violations | ++----------+------------------+-----------------------------------------------------+------------+ +| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | +| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | +| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | ++----------+------------------+-----------------------------------------------------+------------+ + +2. REPORT DETAILS +----------------- +NSTD-1#1 Critical Warning +Unspecified I/O Standard +3 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, done, reset. +Related violations: + +UCIO-1#1 Critical Warning +Unconstrained Logical Port +3 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk, done, reset. +Related violations: + +CFGBVS-1#1 Warning +Missing CFGBVS and CONFIG_VOLTAGE Design Properties +Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: + + set_property CFGBVS value1 [current_design] + #where value1 is either VCCO or GND + + set_property CONFIG_VOLTAGE value2 [current_design] + #where value2 is the voltage provided to configuration bank 0 + +Refer to the device configuration user guide for more information. +Related violations: + + diff --git a/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt new file mode 100644 index 0000000..78ca514 --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt @@ -0,0 +1,526 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:54:50 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_io -file CPU9bits_io_placed.rpt +| Design : CPU9bits +| Device : xc7k160ti +| Speed File : -2L +| Package : fbg484 +| Package Version : FINAL 2012-06-26 +| Package Pin Delay Version : VERS. 2.0 2012-06-26 +------------------------------------------------------------------------------------------------- + +IO Information + +Table of Contents +----------------- +1. Summary +2. IO Assignments by Package Pin + +1. Summary +---------- + ++---------------+ +| Total User IO | ++---------------+ +| 3 | ++---------------+ + + +2. IO Assignments by Package Pin +-------------------------------- + ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| A3 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| A4 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A8 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A9 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| A10 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A11 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| A13 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | +| A14 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A15 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A16 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| A18 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | | +| A19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | +| A20 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | +| A21 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | +| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA1 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA3 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA4 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AA5 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA6 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| AA8 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA9 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA10 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA11 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AA13 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AA14 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA15 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| AA18 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA19 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA20 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA21 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB1 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB2 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB3 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| AB4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| AB5 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB6 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB10 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB11 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB12 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB13 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| AB15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB17 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB18 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| AB20 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB21 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| AB22 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| B1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| B2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B5 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | | +| B6 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | | +| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B8 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B10 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B11 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| B12 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B13 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | +| B14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| B15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B16 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B17 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | | +| B18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | +| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| B20 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | +| B21 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | +| B22 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | +| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| C3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | | +| C4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | | +| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C8 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| C9 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| C10 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| C11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| C12 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C13 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C14 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C15 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| C17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | | +| C18 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | | +| C19 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | +| C20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| C21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| C22 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| D1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| D2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | | +| D6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | | +| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| D9 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| D10 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| D11 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| D12 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | +| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| D14 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | +| D15 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | | +| D16 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | | +| D17 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| D18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| D19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | +| D20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | +| D21 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| D22 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| E3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | | +| E4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | | +| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E8 | | High Range | IO_24_T3_16 | User IO | | 16 | | | | | | | | | | | | | | +| E9 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E11 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| E12 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| E13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| E14 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | +| E15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| E16 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E17 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | +| E19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | +| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| E21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | +| E22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | +| F1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| F2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | | +| F6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | | +| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F8 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| F9 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| F11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| F12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| F13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| F14 | | High Range | IO_6_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | +| F15 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | +| F16 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | +| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| F18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | +| F19 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | +| F20 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | +| F21 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | +| F22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | +| G3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | | +| G4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | | +| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | +| G7 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | +| G8 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| G9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | +| G10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| G11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| G12 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| G13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | +| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| G15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | +| G16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | +| G17 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | +| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | +| G19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| G20 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | +| G21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| G22 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | +| H1 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | | +| H2 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | | +| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H6 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | +| H7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | +| H8 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| H9 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| H10 | | High Range | IO_18_T2_16 | User IO | | 16 | | | | | | | | | | | | | | +| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H12 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | +| H13 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| H14 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | +| H15 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | +| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | +| H17 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | +| H18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | +| H19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | +| H20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| H22 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | +| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J4 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | | +| J5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | +| J6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | +| J7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| J16 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | +| J17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | +| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| J19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | +| J20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| J21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | +| J22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | +| K1 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K2 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| K4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | | +| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | +| K7 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | +| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| K11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | +| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| K16 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | +| K17 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| K18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| K19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | +| K20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| K21 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| K22 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | +| L1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L3 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| L5 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| L6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | +| L7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | +| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | +| L12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | +| L13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| L16 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| L18 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | +| L19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| L20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| L21 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | +| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M1 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| M2 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| M3 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| M4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| M5 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| M6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | +| M7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | +| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| M11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | +| M12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | +| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M16 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | +| M17 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| M18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| M20 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | +| M21 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | +| M22 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| N1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| N2 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| N3 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | +| N4 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| N5 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | +| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | +| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| N17 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | +| N18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | +| N20 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | +| N21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| N22 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | +| P1 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| P2 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P4 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| P5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| P6 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | +| P7 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | +| P8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| P16 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | +| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | +| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | +| P19 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | +| P20 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | +| P21 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | +| P22 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | +| R1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| R2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| R3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R4 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| R5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| R6 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| R7 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | +| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | +| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | +| R16 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| R17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | +| R18 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | +| R19 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | +| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| R21 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | +| R22 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | +| T1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| T2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| T3 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| T5 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| T6 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | | +| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T8 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| T9 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| T10 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| T11 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | | +| T15 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| T16 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | +| T20 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| T21 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| T22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| U1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | +| U2 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| U3 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U5 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| U6 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| U7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| U8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| U9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| U10 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| U11 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | +| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| U15 | reset | High Range | IO_L24N_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| U16 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| U19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| U20 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| U21 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| U22 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V2 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| V3 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| V4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| V5 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | | +| V6 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| V7 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| V8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| V9 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| V10 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| V14 | done | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| V15 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| V17 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | +| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| V19 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| V20 | clk | High Range | IO_L11P_T1_SRCC_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | +| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| V22 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| W1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W2 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | +| W3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | +| W4 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | +| W5 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| W6 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| W7 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W9 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| W10 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| W11 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | +| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | +| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| W14 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| W15 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| W16 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| W19 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W20 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| W21 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| W22 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y2 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y3 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y4 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | +| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y6 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y7 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y8 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y9 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | +| Y11 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y12 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y13 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | +| Y14 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | +| Y16 | | High Range | IO_L21N_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y17 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y18 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y19 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | +| Y21 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | +| Y22 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | ++------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ +* Default value +** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. + + diff --git a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb new file mode 100644 index 0000000..e0f8955 Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt new file mode 100644 index 0000000..7b68c11 --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt @@ -0,0 +1,50 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +-------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:55:21 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx +| Design : CPU9bits +| Device : xc7k160tifbg484-2L +| Speed File : -2L +| Design State : Fully Routed +-------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Report Methodology + +Table of Contents +----------------- +1. REPORT SUMMARY +2. REPORT DETAILS + +1. REPORT SUMMARY +----------------- + Netlist: netlist + Floorplan: design_1 + Design limits: + Max violations: + Violations found: 3 ++-----------+----------+-----------------------------+------------+ +| Rule | Severity | Description | Violations | ++-----------+----------+-----------------------------+------------+ +| TIMING-17 | Warning | Non-clocked sequential cell | 3 | ++-----------+----------+-----------------------------+------------+ + +2. REPORT DETAILS +----------------- +TIMING-17#1 Warning +Non-clocked sequential cell +The clock pin FetchU/PC/Dout_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#2 Warning +Non-clocked sequential cell +The clock pin FetchU/PC/Dout_reg[1]/C is not reached by a timing clock +Related violations: + +TIMING-17#3 Warning +Non-clocked sequential cell +The clock pin FetchU/PC/Dout_reg[2]/C is not reached by a timing clock +Related violations: + + diff --git a/lab2CA.runs/impl_1/CPU9bits_opt.dcp b/lab2CA.runs/impl_1/CPU9bits_opt.dcp new file mode 100644 index 0000000..6719336 Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_opt.dcp differ diff --git a/lab2CA.runs/impl_1/CPU9bits_placed.dcp b/lab2CA.runs/impl_1/CPU9bits_placed.dcp new file mode 100644 index 0000000..25b333a Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_placed.dcp differ diff --git a/lab2CA.runs/impl_1/CPU9bits_power_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_power_routed.rpt new file mode 100644 index 0000000..7baf9a5 --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_power_routed.rpt @@ -0,0 +1,146 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +---------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:55:21 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx +| Design : CPU9bits +| Device : xc7k160tifbg484-2L +| Design State : routed +| Grade : industrial +| Process : typical +| Characterization : Production +---------------------------------------------------------------------------------------------------------------------------------------------- + +Power Report + +Table of Contents +----------------- +1. Summary +1.1 On-Chip Components +1.2 Power Supply Summary +1.3 Confidence Level +2. Settings +2.1 Environment +2.2 Clock Constraints +3. Detailed Reports +3.1 By Hierarchy + +1. Summary +---------- + ++--------------------------+--------------+ +| Total On-Chip Power (W) | 0.198 | +| Design Power Budget (W) | Unspecified* | +| Power Budget Margin (W) | NA | +| Dynamic (W) | 0.111 | +| Device Static (W) | 0.086 | +| Effective TJA (C/W) | 2.5 | +| Max Ambient (C) | 99.5 | +| Junction Temperature (C) | 25.5 | +| Confidence Level | Low | +| Setting File | --- | +| Simulation Activity File | --- | +| Design Nets Matched | NA | ++--------------------------+--------------+ +* Specify Design Power Budget using, set_operating_conditions -design_power_budget + + +1.1 On-Chip Components +---------------------- + ++----------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++----------------+-----------+----------+-----------+-----------------+ +| Slice Logic | 0.019 | 10 | --- | --- | +| LUT as Logic | 0.012 | 2 | 101400 | <0.01 | +| BUFG | 0.005 | 1 | 32 | 3.13 | +| Register | 0.001 | 3 | 202800 | <0.01 | +| Others | 0.000 | 2 | --- | --- | +| Signals | 0.018 | 7 | --- | --- | +| I/O | 0.074 | 3 | 285 | 1.05 | +| Static Power | 0.086 | | | | +| Total | 0.198 | | | | ++----------------+-----------+----------+-----------+-----------------+ + + +1.2 Power Supply Summary +------------------------ + ++-----------+-------------+-----------+-------------+------------+ +| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | ++-----------+-------------+-----------+-------------+------------+ +| Vccint | 0.950 | 0.070 | 0.047 | 0.023 | +| Vccaux | 1.800 | 0.022 | 0.005 | 0.016 | +| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | +| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | +| Vcco18 | 1.800 | 0.033 | 0.032 | 0.001 | +| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | +| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | +| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | +| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccbram | 0.950 | 0.001 | 0.000 | 0.001 | +| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | +| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | +| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | +| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 | ++-----------+-------------+-----------+-------------+------------+ + + +1.3 Confidence Level +-------------------- + ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| User Input Data | Confidence | Details | Action | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ +| Design implementation state | High | Design is routed | | +| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | +| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | +| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | +| Device models | High | Device models are Production | | +| | | | | +| Overall confidence level | Low | | | ++-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ + + +2. Settings +----------- + +2.1 Environment +--------------- + ++-----------------------+--------------------------+ +| Ambient Temp (C) | 25.0 | +| ThetaJA (C/W) | 2.5 | +| Airflow (LFM) | 250 | +| Heat Sink | medium (Medium Profile) | +| ThetaSA (C/W) | 4.2 | +| Board Selection | medium (10"x10") | +| # of Board Layers | 12to15 (12 to 15 Layers) | +| Board Temperature (C) | 25.0 | ++-----------------------+--------------------------+ + + +2.2 Clock Constraints +--------------------- + ++-------+--------+-----------------+ +| Clock | Domain | Constraint (ns) | ++-------+--------+-----------------+ + + +3. Detailed Reports +------------------- + +3.1 By Hierarchy +---------------- + ++----------+-----------+ +| Name | Power (W) | ++----------+-----------+ +| CPU9bits | 0.111 | +| FetchU | 0.020 | +| PC | 0.020 | ++----------+-----------+ + + diff --git a/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb b/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb new file mode 100644 index 0000000..7f38109 Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_route_status.pb b/lab2CA.runs/impl_1/CPU9bits_route_status.pb new file mode 100644 index 0000000..e975e2c Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_route_status.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_route_status.rpt b/lab2CA.runs/impl_1/CPU9bits_route_status.rpt new file mode 100644 index 0000000..ede565f --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_route_status.rpt @@ -0,0 +1,11 @@ +Design Route Status + : # nets : + ------------------------------------------- : ----------- : + # of logical nets.......................... : 15 : + # of nets not needing routing.......... : 7 : + # of internally routed nets........ : 7 : + # of routable nets..................... : 8 : + # of fully routed nets............. : 8 : + # of nets with routing errors.......... : 0 : + ------------------------------------------- : ----------- : + diff --git a/lab2CA.runs/impl_1/CPU9bits_routed.dcp b/lab2CA.runs/impl_1/CPU9bits_routed.dcp new file mode 100644 index 0000000..ef49416 Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_routed.dcp differ diff --git a/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb b/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb new file mode 100644 index 0000000..4526e93 --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb @@ -0,0 +1,2 @@ + +2012.4’)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt new file mode 100644 index 0000000..083cc4d --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt @@ -0,0 +1,173 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:55:21 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation +| Design : CPU9bits +| Device : 7k160ti-fbg484 +| Speed File : -2L PRODUCTION 1.12 2017-02-17 +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + +Timing Summary Report + +------------------------------------------------------------------------------------------------ +| Timer Settings +| -------------- +------------------------------------------------------------------------------------------------ + + Enable Multi Corner Analysis : Yes + Enable Pessimism Removal : Yes + Pessimism Removal Resolution : Nearest Common Node + Enable Input Delay Default Clock : No + Enable Preset / Clear Arcs : No + Disable Flight Delays : No + Ignore I/O Paths : No + Timing Early Launch at Borrowing Latches : false + + Corner Analyze Analyze + Name Max Paths Min Paths + ------ --------- --------- + Slow Yes Yes + Fast Yes Yes + + + +check_timing report + +Table of Contents +----------------- +1. checking no_clock +2. checking constant_clock +3. checking pulse_width_clock +4. checking unconstrained_internal_endpoints +5. checking no_input_delay +6. checking no_output_delay +7. checking multiple_clock +8. checking generated_clocks +9. checking loops +10. checking partial_input_delay +11. checking partial_output_delay +12. checking latch_loops + +1. checking no_clock +-------------------- + There are 3 register/latch pins with no clock driven by root clock pin: clk (HIGH) + + +2. checking constant_clock +-------------------------- + There are 0 register/latch pins with constant_clock. + + +3. checking pulse_width_clock +----------------------------- + There are 0 register/latch pins which need pulse_width check + + +4. checking unconstrained_internal_endpoints +-------------------------------------------- + There are 3 pins that are not constrained for maximum delay. (HIGH) + + There are 0 pins that are not constrained for maximum delay due to constant clock. + + +5. checking no_input_delay +-------------------------- + There is 1 input port with no input delay specified. (HIGH) + + There are 0 input ports with no input delay but user has a false path constraint. + + +6. checking no_output_delay +--------------------------- + There is 1 port with no output delay specified. (HIGH) + + There are 0 ports with no output delay but user has a false path constraint + + There are 0 ports with no output delay but with a timing clock defined on it or propagating through it + + +7. checking multiple_clock +-------------------------- + There are 0 register/latch pins with multiple clocks. + + +8. checking generated_clocks +---------------------------- + There are 0 generated clocks that are not connected to a clock source. + + +9. checking loops +----------------- + There are 0 combinational loops in the design. + + +10. checking partial_input_delay +-------------------------------- + There are 0 input ports with partial input delay specified. + + +11. checking partial_output_delay +--------------------------------- + There are 0 ports with partial output delay specified. + + +12. checking latch_loops +------------------------ + There are 0 combinational latch loops in the design through latch input + + + +------------------------------------------------------------------------------------------------ +| Design Timing Summary +| --------------------- +------------------------------------------------------------------------------------------------ + + WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints + ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + NA NA NA NA NA NA NA NA NA NA NA NA + + +There are no user specified timing constraints. + + +------------------------------------------------------------------------------------------------ +| Clock Summary +| ------------- +------------------------------------------------------------------------------------------------ + + +------------------------------------------------------------------------------------------------ +| Intra Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints +----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- + + +------------------------------------------------------------------------------------------------ +| Inter Clock Table +| ----------------- +------------------------------------------------------------------------------------------------ + +From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Other Path Groups Table +| ----------------------- +------------------------------------------------------------------------------------------------ + +Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints +---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- + + +------------------------------------------------------------------------------------------------ +| Timing Details +| -------------- +------------------------------------------------------------------------------------------------ + + diff --git a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb new file mode 100644 index 0000000..cc59513 Binary files /dev/null and b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt new file mode 100644 index 0000000..c80eb1c --- /dev/null +++ b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt @@ -0,0 +1,205 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:54:50 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb +| Design : CPU9bits +| Device : 7k160tifbg484-2L +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 2 | 0 | 101400 | <0.01 | +| LUT as Logic | 2 | 0 | 101400 | <0.01 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 3 | 0 | 202800 | <0.01 | +| Register as Flip Flop | 3 | 0 | 202800 | <0.01 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 3 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 1 | 0 | 25350 | <0.01 | +| SLICEL | 1 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 2 | 0 | 101400 | <0.01 | +| using O5 output only | 0 | | | | +| using O6 output only | 0 | | | | +| using O5 and O6 | 2 | | | | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 3 | 0 | 202800 | <0.01 | +| Register driven from within the Slice | 3 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 1 | | 25350 | <0.01 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 3 | 0 | 285 | 1.05 | +| IOB Master Pads | 1 | | | | +| IOB Slave Pads | 1 | | | | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 275 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 1 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 3 | Flop & Latch | +| LUT3 | 2 | LUT | +| IBUF | 2 | IO | +| OBUF | 1 | IO | +| LUT4 | 1 | LUT | +| LUT2 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml new file mode 100644 index 0000000..9ef2a2c --- /dev/null +++ b/lab2CA.runs/impl_1/gen_run.xml @@ -0,0 +1,167 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lab2CA.runs/impl_1/htr.txt b/lab2CA.runs/impl_1/htr.txt new file mode 100644 index 0000000..a32836e --- /dev/null +++ b/lab2CA.runs/impl_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log CPU9bits.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace diff --git a/lab2CA.runs/impl_1/init_design.pb b/lab2CA.runs/impl_1/init_design.pb index 0d2ab79..89f88ee 100644 Binary files a/lab2CA.runs/impl_1/init_design.pb and b/lab2CA.runs/impl_1/init_design.pb differ diff --git a/lab2CA.runs/impl_1/opt_design.pb b/lab2CA.runs/impl_1/opt_design.pb index 927ab77..f807a89 100644 Binary files a/lab2CA.runs/impl_1/opt_design.pb and b/lab2CA.runs/impl_1/opt_design.pb differ diff --git a/lab2CA.runs/impl_1/place_design.pb b/lab2CA.runs/impl_1/place_design.pb index 0bd0bfa..b432a96 100644 Binary files a/lab2CA.runs/impl_1/place_design.pb and b/lab2CA.runs/impl_1/place_design.pb differ diff --git a/lab2CA.runs/impl_1/route_design.pb b/lab2CA.runs/impl_1/route_design.pb index 7a02ef6..2bf8ea8 100644 Binary files a/lab2CA.runs/impl_1/route_design.pb and b/lab2CA.runs/impl_1/route_design.pb differ diff --git a/lab2CA.runs/impl_1/vivado.jou b/lab2CA.runs/impl_1/vivado.jou new file mode 100644 index 0000000..b47ea4f --- /dev/null +++ b/lab2CA.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Wed Mar 20 10:54:16 2019 +# Process ID: 6632 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 +# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source CPU9bits.tcl -notrace diff --git a/lab2CA.runs/impl_1/vivado.pb b/lab2CA.runs/impl_1/vivado.pb new file mode 100644 index 0000000..29cdb3f Binary files /dev/null and b/lab2CA.runs/impl_1/vivado.pb differ diff --git a/lab2CA.runs/synth_1/CPU9bits.dcp b/lab2CA.runs/synth_1/CPU9bits.dcp new file mode 100644 index 0000000..fa5ed37 Binary files /dev/null and b/lab2CA.runs/synth_1/CPU9bits.dcp differ diff --git a/lab2CA.runs/synth_1/CPU9bits.tcl b/lab2CA.runs/synth_1/CPU9bits.tcl new file mode 100644 index 0000000..fd7a162 --- /dev/null +++ b/lab2CA.runs/synth_1/CPU9bits.tcl @@ -0,0 +1,60 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +create_project -in_memory -part xc7k160tifbg484-2L + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project] +set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib { + C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v + C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v + C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v + C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v + C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v + C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v + C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v + C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v +} +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top CPU9bits -part xc7k160tifbg484-2L + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef CPU9bits.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/lab2CA.runs/synth_1/CPU9bits.vds b/lab2CA.runs/synth_1/CPU9bits.vds new file mode 100644 index 0000000..5b60a73 --- /dev/null +++ b/lab2CA.runs/synth_1/CPU9bits.vds @@ -0,0 +1,494 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Wed Mar 20 10:53:36 2019 +# Process ID: 12136 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 +# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source CPU9bits.tcl -notrace +Command: synth_design -top CPU9bits -part xc7k160tifbg484-2L +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 8176 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 359.945 ; gain = 102.359 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] +INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] +INFO: [Synth 8-6155] done synthesizing module 'instructionMemory' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] +INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] +WARNING: [Synth 8-567] referenced signal 'clk' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30] +WARNING: [Synth 8-567] referenced signal 'memory' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30] +WARNING: [Synth 8-567] referenced signal 'writeEnable' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30] +WARNING: [Synth 8-567] referenced signal 'writeData' should be on the sensitivity list [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:30] +INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] +INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] +INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268] +INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] +INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] +INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] +INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412] +INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] +INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] +INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] +INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] +INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] +INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] +INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] +INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342] +INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] +INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] +INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] +INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] +INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] +INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] +INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] +INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] +INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] +INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] +INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] +INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] +INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] +INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] +INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] +INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] +INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] +INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] +INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] +INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] +INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] +INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541] +INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] +WARNING: [Synth 8-3848] Net result_M in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +WARNING: [Synth 8-3848] Net result_N in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +WARNING: [Synth 8-3848] Net result_O in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +WARNING: [Synth 8-3848] Net result_P in module/entity ALU does not have driver. [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:11] +INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] +INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] +INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] +INFO: [Synth 8-6157] synthesizing module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:965] +INFO: [Synth 8-6155] done synthesizing module 'sign_extend_2bit' (25#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:965] +WARNING: [Synth 8-689] width (3) of port connection 'A' does not match port width (2) of module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:89] +INFO: [Synth 8-6157] synthesizing module 'sign_extend_4bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1035] +INFO: [Synth 8-6155] done synthesizing module 'sign_extend_4bit' (26#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1035] +WARNING: [Synth 8-689] width (5) of port connection 'A' does not match port width (4) of module 'sign_extend_4bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:93] +INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356] +INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (27#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] +WARNING: [Synth 8-689] width (3) of port connection 'A' does not match port width (2) of module 'sign_extend_2bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:112] +INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (28#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] +WARNING: [Synth 8-3331] design shift_right_arithmetic has unconnected port A[0] +WARNING: [Synth 8-3331] design shift_right_logical has unconnected port A[0] +WARNING: [Synth 8-3331] design shift_left has unconnected port A[8] +WARNING: [Synth 8-3331] design instructionMemory has unconnected port clk +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tifbg484-2L +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 415.844 ; gain = 158.258 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7k160tifbg484-2L +INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5) +INFO: [Synth 8-5546] ROM "memory_reg[15]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[14]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[13]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[12]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[11]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[10]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[9]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[8]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[7]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[6]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[5]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[4]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[3]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[2]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[1]" won't be mapped to RAM because it is too sparse +INFO: [Synth 8-5546] ROM "memory_reg[0]" won't be mapped to RAM because it is too sparse +WARNING: [Synth 8-327] inferring latch for variable 'readData_reg' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[15]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[14]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[13]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[12]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[11]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[10]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[9]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[8]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[7]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[6]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[5]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[4]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[3]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[2]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[1]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +WARNING: [Synth 8-327] inferring latch for variable 'memory_reg[0]' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:32] +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 446.785 ; gain = 189.199 +--------------------------------------------------------------------------------- +INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_2bit) to 'SE3' + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 144 ++---Registers : + 9 Bit Registers := 5 ++---Muxes : + 7 Input 9 Bit Muxes := 1 + 2 Input 9 Bit Muxes := 22 + 4 Input 9 Bit Muxes := 2 + 2 Input 4 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 + 15 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 2 + 15 Input 3 Bit Muxes := 1 + 16 Input 1 Bit Muxes := 16 + 2 Input 1 Bit Muxes := 17 + 3 Input 1 Bit Muxes := 16 + 15 Input 1 Bit Muxes := 5 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module instructionMemory +Detailed RTL Component Info : ++---Muxes : + 7 Input 9 Bit Muxes := 1 +Module dataMemory +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 16 + 16 Input 1 Bit Muxes := 16 + 2 Input 1 Bit Muxes := 16 + 3 Input 1 Bit Muxes := 16 +Module decoder +Detailed RTL Component Info : ++---Muxes : + 2 Input 4 Bit Muxes := 1 + 4 Input 4 Bit Muxes := 1 +Module register +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 +Module mux_4_1 +Detailed RTL Component Info : ++---Muxes : + 4 Input 9 Bit Muxes := 1 +Module add_1bit +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module mux_2_1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +Module ControlUnit +Detailed RTL Component Info : ++---Muxes : + 15 Input 4 Bit Muxes := 1 + 2 Input 3 Bit Muxes := 2 + 15 Input 3 Bit Muxes := 1 + 15 Input 1 Bit Muxes := 5 +Module bit1_mux_2_1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/readData_reg[0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[15][0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[14][0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[13][0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[12][0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[11][0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[10][0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[9][0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[8][0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[7][0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][8]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][7]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][6]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][5]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][4]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][3]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][2]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][1]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[6][0]) is unused and will be removed from module CPU9bits. +WARNING: [Synth 8-3332] Sequential element (dM/memory_reg[5][8]) is unused and will be removed from module CPU9bits. +INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 594.980 ; gain = 337.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFG | 1| +|2 |LUT2 | 1| +|3 |LUT3 | 2| +|4 |LUT4 | 1| +|5 |FDRE | 3| +|6 |IBUF | 2| +|7 |OBUF | 1| ++------+-----+------+ + +Report Instance Areas: ++------+---------+----------+------+ +| |Instance |Module |Cells | ++------+---------+----------+------+ +|1 |top | | 11| +|2 | FetchU |FetchUnit | 7| +|3 | PC |register | 7| ++------+---------+----------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 185 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395 +Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 594.980 ; gain = 337.395 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.789 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +87 Infos, 132 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 681.789 ; gain = 431.723 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 681.789 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Wed Mar 20 10:54:03 2019... diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb new file mode 100644 index 0000000..cc59513 Binary files /dev/null and b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb differ diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt new file mode 100644 index 0000000..e0a53ec --- /dev/null +++ b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt @@ -0,0 +1,179 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Wed Mar 20 10:54:03 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb +| Design : CPU9bits +| Device : 7k160tifbg484-2L +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 2 | 0 | 101400 | <0.01 | +| LUT as Logic | 2 | 0 | 101400 | <0.01 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 3 | 0 | 202800 | <0.01 | +| Register as Flip Flop | 3 | 0 | 202800 | <0.01 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 3 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 3 | 0 | 285 | 1.05 | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 275 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 1 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 3 | Flop & Latch | +| LUT3 | 2 | LUT | +| IBUF | 2 | IO | +| OBUF | 1 | IO | +| LUT4 | 1 | LUT | +| LUT2 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..23648ce --- /dev/null +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -0,0 +1,99 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lab2CA.runs/synth_1/htr.txt b/lab2CA.runs/synth_1/htr.txt new file mode 100644 index 0000000..641d4cb --- /dev/null +++ b/lab2CA.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log CPU9bits.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl diff --git a/lab2CA.runs/synth_1/vivado.jou b/lab2CA.runs/synth_1/vivado.jou new file mode 100644 index 0000000..03aec58 --- /dev/null +++ b/lab2CA.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Wed Mar 20 10:53:36 2019 +# Process ID: 12136 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 +# Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source CPU9bits.tcl -notrace diff --git a/lab2CA.runs/synth_1/vivado.pb b/lab2CA.runs/synth_1/vivado.pb index 52bd0cf..3021c23 100644 Binary files a/lab2CA.runs/synth_1/vivado.pb and b/lab2CA.runs/synth_1/vivado.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb_vlog.prj index 72b8571..34fbace 100644 --- a/lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb_vlog.prj +++ b/lab2CA.sim/sim_1/behav/xsim/CPU9bits_tb_vlog.prj @@ -5,6 +5,8 @@ verilog xil_defaultlib \ "../../../../lab2CA.srcs/sources_1/new/ControlUnit.v" \ "../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \ "../../../../lab2CA.srcs/sources_1/new/RegFile.v" \ +"../../../../lab2CA.srcs/sources_1/new/dataMemory.v" \ +"../../../../lab2CA.srcs/sources_1/new/instructionMemory.v" \ "../../../../lab2CA.srcs/sources_1/new/CPU9bits.v" \ # compile glbl module diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index a95fa0b..b34159f 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 16 14:36:18 2019 -# Process ID: 18656 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +# Start of session at: Wed Mar 20 11:12:18 2019 +# Process ID: 4156 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/JoseIgnacio/CA -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_14548.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_14548.backup.jou deleted file mode 100644 index 39026d0..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_14548.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 16 13:13:49 2019 -# Process ID: 14548 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_18656.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_18656.backup.jou new file mode 100644 index 0000000..a95fa0b --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_18656.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Mar 16 14:36:18 2019 +# Process ID: 18656 +# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/JoseIgnacio/CA -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_7732.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_7548.backup.jou similarity index 71% rename from lab2CA.sim/sim_1/behav/xsim/webtalk_7732.backup.jou rename to lab2CA.sim/sim_1/behav/xsim/webtalk_7548.backup.jou index 3049660..b0f6387 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_7732.backup.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_7548.backup.jou @@ -2,11 +2,11 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 16 13:12:04 2019 -# Process ID: 7732 +# Start of session at: Wed Mar 20 11:11:12 2019 +# Process ID: 7548 # Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index 937bfab..e5499fd 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xelab.pb and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c index 65d8519..f7bbd09 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/obj/xsim_1.c @@ -46,19 +46,12 @@ typedef void (*funcp)(char *, char *); extern int main(int, char**); extern void execute_2(char*, char *); extern void execute_3(char*, char *); -extern void execute_140(char*, char *); -extern void execute_343(char*, char *); -extern void execute_344(char*, char *); -extern void execute_345(char*, char *); +extern void execute_146(char*, char *); +extern void execute_351(char*, char *); +extern void execute_352(char*, char *); extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); -extern void execute_325(char*, char *); -extern void execute_326(char*, char *); -extern void execute_328(char*, char *); -extern void execute_329(char*, char *); -extern void execute_330(char*, char *); extern void execute_331(char*, char *); extern void execute_332(char*, char *); -extern void execute_333(char*, char *); extern void execute_334(char*, char *); extern void execute_335(char*, char *); extern void execute_336(char*, char *); @@ -68,54 +61,66 @@ extern void execute_339(char*, char *); extern void execute_340(char*, char *); extern void execute_341(char*, char *); extern void execute_342(char*, char *); -extern void execute_145(char*, char *); -extern void execute_146(char*, char *); -extern void execute_147(char*, char *); -extern void execute_148(char*, char *); -extern void execute_149(char*, char *); -extern void execute_150(char*, char *); -extern void execute_151(char*, char *); -extern void execute_7(char*, char *); -extern void execute_9(char*, char *); -extern void execute_17(char*, char *); -extern void execute_171(char*, char *); -extern void execute_173(char*, char *); -extern void execute_174(char*, char *); -extern void execute_152(char*, char *); -extern void execute_153(char*, char *); -extern void execute_34(char*, char *); -extern void execute_283(char*, char *); -extern void execute_284(char*, char *); -extern void execute_212(char*, char *); -extern void execute_193(char*, char *); -extern void execute_233(char*, char *); -extern void execute_234(char*, char *); -extern void execute_235(char*, char *); -extern void execute_236(char*, char *); -extern void execute_237(char*, char *); -extern void execute_238(char*, char *); -extern void execute_280(char*, char *); -extern void execute_281(char*, char *); -extern void execute_102(char*, char *); -extern void execute_104(char*, char *); -extern void execute_303(char*, char *); -extern void execute_304(char*, char *); -extern void execute_122(char*, char *); -extern void execute_142(char*, char *); -extern void execute_143(char*, char *); -extern void execute_144(char*, char *); +extern void execute_343(char*, char *); +extern void execute_344(char*, char *); +extern void execute_345(char*, char *); extern void execute_346(char*, char *); extern void execute_347(char*, char *); extern void execute_348(char*, char *); extern void execute_349(char*, char *); extern void execute_350(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_151(char*, char *); +extern void execute_152(char*, char *); +extern void execute_153(char*, char *); +extern void execute_154(char*, char *); +extern void execute_155(char*, char *); +extern void execute_156(char*, char *); +extern void execute_157(char*, char *); +extern void execute_13(char*, char *); +extern void execute_15(char*, char *); +extern void execute_23(char*, char *); +extern void execute_177(char*, char *); +extern void execute_179(char*, char *); +extern void execute_180(char*, char *); +extern void execute_158(char*, char *); +extern void execute_159(char*, char *); +extern void execute_40(char*, char *); +extern void execute_289(char*, char *); +extern void execute_290(char*, char *); +extern void execute_218(char*, char *); +extern void execute_199(char*, char *); +extern void execute_239(char*, char *); +extern void execute_240(char*, char *); +extern void execute_241(char*, char *); +extern void execute_242(char*, char *); +extern void execute_243(char*, char *); +extern void execute_244(char*, char *); +extern void execute_286(char*, char *); +extern void execute_287(char*, char *); +extern void execute_108(char*, char *); +extern void execute_110(char*, char *); +extern void execute_309(char*, char *); +extern void execute_310(char*, char *); +extern void execute_128(char*, char *); +extern void execute_148(char*, char *); +extern void execute_149(char*, char *); +extern void execute_150(char*, char *); +extern void execute_353(char*, char *); +extern void execute_354(char*, char *); +extern void execute_355(char*, char *); +extern void execute_356(char*, char *); +extern void execute_357(char*, char *); extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); -funcp funcTab[66] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_140, (funcp)execute_343, (funcp)execute_344, (funcp)execute_345, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_325, (funcp)execute_326, (funcp)execute_328, (funcp)execute_329, (funcp)execute_330, (funcp)execute_331, (funcp)execute_332, (funcp)execute_333, (funcp)execute_334, (funcp)execute_335, (funcp)execute_336, (funcp)execute_337, (funcp)execute_338, (funcp)execute_339, (funcp)execute_340, (funcp)execute_341, (funcp)execute_342, (funcp)execute_145, (funcp)execute_146, (funcp)execute_147, (funcp)execute_148, (funcp)execute_149, (funcp)execute_150, (funcp)execute_151, (funcp)execute_7, (funcp)execute_9, (funcp)execute_17, (funcp)execute_171, (funcp)execute_173, (funcp)execute_174, (funcp)execute_152, (funcp)execute_153, (funcp)execute_34, (funcp)execute_283, (funcp)execute_284, (funcp)execute_212, (funcp)execute_193, (funcp)execute_233, (funcp)execute_234, (funcp)execute_235, (funcp)execute_236, (funcp)execute_237, (funcp)execute_238, (funcp)execute_280, (funcp)execute_281, (funcp)execute_102, (funcp)execute_104, (funcp)execute_303, (funcp)execute_304, (funcp)execute_122, (funcp)execute_142, (funcp)execute_143, (funcp)execute_144, (funcp)execute_346, (funcp)execute_347, (funcp)execute_348, (funcp)execute_349, (funcp)execute_350, (funcp)vlog_transfunc_eventcallback}; -const int NumRelocateId= 66; +funcp funcTab[71] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_146, (funcp)execute_351, (funcp)execute_352, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_331, (funcp)execute_332, (funcp)execute_334, (funcp)execute_335, (funcp)execute_336, (funcp)execute_337, (funcp)execute_338, (funcp)execute_339, (funcp)execute_340, (funcp)execute_341, (funcp)execute_342, (funcp)execute_343, (funcp)execute_344, (funcp)execute_345, (funcp)execute_346, (funcp)execute_347, (funcp)execute_348, (funcp)execute_349, (funcp)execute_350, (funcp)execute_6, (funcp)execute_7, (funcp)execute_9, (funcp)execute_10, (funcp)execute_151, (funcp)execute_152, (funcp)execute_153, (funcp)execute_154, (funcp)execute_155, (funcp)execute_156, (funcp)execute_157, (funcp)execute_13, (funcp)execute_15, (funcp)execute_23, (funcp)execute_177, (funcp)execute_179, (funcp)execute_180, (funcp)execute_158, (funcp)execute_159, (funcp)execute_40, (funcp)execute_289, (funcp)execute_290, (funcp)execute_218, (funcp)execute_199, (funcp)execute_239, (funcp)execute_240, (funcp)execute_241, (funcp)execute_242, (funcp)execute_243, (funcp)execute_244, (funcp)execute_286, (funcp)execute_287, (funcp)execute_108, (funcp)execute_110, (funcp)execute_309, (funcp)execute_310, (funcp)execute_128, (funcp)execute_148, (funcp)execute_149, (funcp)execute_150, (funcp)execute_353, (funcp)execute_354, (funcp)execute_355, (funcp)execute_356, (funcp)execute_357, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 71; void relocate(char *dp) { - iki_relocate(dp, "xsim.dir/CPU9bits_tb_behav/xsim.reloc", (void **)funcTab, 66); + iki_relocate(dp, "xsim.dir/CPU9bits_tb_behav/xsim.reloc", (void **)funcTab, 71); /*Populate the transaction function pointer field in the whole net structure */ } diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..9681607 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
+
+ + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+ +
+
+ + + + + +
+
+
+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl index aa790df..e1d5488 100644 --- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl @@ -1,10 +1,10 @@ -webtalk_init -webtalk_dir C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/ webtalk_register_client -client project -webtalk_add_data -client project -key date_generated -value "Sat Mar 16 14:38:26 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key date_generated -value "Wed Mar 20 12:06:50 2019" -context "software_version_and_target_device" webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" -webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" @@ -12,17 +12,17 @@ webtalk_add_data -client project -key target_family -value "not_applicable" -con webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" -webtalk_add_data -client project -key random_id -value "17336daf-0d92-4f07-b4a4-ff1c52043edb" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" -webtalk_add_data -client project -key project_iteration -value "59" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "55" -context "software_version_and_target_device" webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" -webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz" -context "user_environment" -webtalk_add_data -client project -key cpu_speed -value "2594 MHz" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" -webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" webtalk_register_client -client xsim -webtalk_add_data -client xsim -key File_Counter -value "7" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key File_Counter -value "9" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options" @@ -30,13 +30,13 @@ webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\co webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options" webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options" -webtalk_add_data -client xsim -key Simulation_Image_Code -value "93 KB" -context "xsim\\usage" -webtalk_add_data -client xsim -key Simulation_Image_Data -value "15 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Code -value "98 KB" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Image_Data -value "16 KB" -context "xsim\\usage" webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Processes -value "234" -context "xsim\\usage" -webtalk_add_data -client xsim -key Total_Instances -value "121" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Processes -value "241" -context "xsim\\usage" +webtalk_add_data -client xsim -key Total_Instances -value "123" -context "xsim\\usage" webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage" -webtalk_add_data -client xsim -key Compiler_Time -value "1.01_sec" -context "xsim\\usage" -webtalk_add_data -client xsim -key Compiler_Memory -value "45588_KB" -context "xsim\\usage" -webtalk_transmit -clientid 3212063844 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_add_data -client xsim -key Compiler_Time -value "0.92_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Compiler_Memory -value "47216_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2850620423 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem index e981b0e..2636375 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb index 8e95672..8eae0ad 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb and b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index 20730dc..a6b2452 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -139,7 +139,6 @@ module CPU9bits( endmodule module CPU9bits_tb(); - reg [8:0] instruction; reg clk, reset; wire done; @@ -151,31 +150,37 @@ module CPU9bits_tb(); end CPU9bits CPU9bits0( - .instr(instruction), .reset(reset), .clk(clk), .done(done)); initial begin - instruction = 9'b000100000; reset = 1'b1; - #10 + #15 reset = 1'b0; - #10 - instruction = 9'b000101000; - #10 - instruction = 9'b010100010; - #10 - instruction = 9'b111100000; - #10 - instruction = 9'b111100000; - #10 - instruction = 9'b001101000; - #10 - instruction = 9'b010001000; - #10 - instruction = 9'b000000000; - #10 + #500 + + + +// instruction = 9'b000100000; +// reset = 1'b1; +// #10 +// reset = 1'b0; +// #10 +// instruction = 9'b000101000; +// #10 +// instruction = 9'b010100010; +// #10 +// instruction = 9'b111100000; +// #10 +// instruction = 9'b111100000; +// #10 +// instruction = 9'b001101000; +// #10 +// instruction = 9'b010001000; +// #10 +// instruction = 9'b000000000; +// #10 $finish; end diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v index eeec080..ca27e07 100644 --- a/lab2CA.srcs/sources_1/new/instructionMemory.v +++ b/lab2CA.srcs/sources_1/new/instructionMemory.v @@ -10,12 +10,32 @@ module instructionMemory( initial begin //Equation Solver - memory[0] <= 9'b000100000; - memory[1] <= 9'b000101000; - memory[2] <= 9'b010100010; - memory[3] <= 9'b111100000; - memory[4] <= 9'b111100000; - memory[5] <= 9'b000000000; + memory[0] <= 9'b000000000; + memory[1] <= 9'b000100000; //load + memory[2] <= 9'b000101000; //load + memory[3] <= 9'b010100010; //add + memory[4] <= 9'b111100000; //shift left + memory[5] <= 9'b111100000; //shift left + + //Testing all instructions + memory[6] <= 9'b010100011; //sub + memory[7] <= 9'b011001011; //addi + memory[8] <= 9'b011110000; //slt + memory[9] <= 9'b110111000; //nor + memory[10] <= 9'b111011000; //or + memory[11] <= 9'b111011001; //and + memory[12] <= 9'b111111000; //sll + memory[13] <= 9'b111111001; //srl + // memory[14] <= 9'b100101100; //j + memory[14] <= 9'b110001001; //beq + memory[15] <= 9'b100001000; //jr + + + + + memory[16] <= 9'b000000000; + + end diff --git a/lab2CA.xpr b/lab2CA.xpr index 97321c9..241767e 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - +