From cadbc4dd2575532c1c5bda66ffd1d48bea1e93d9 Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 15:20:12 -0500 Subject: [PATCH] Added 9-bit NOT --- lab2CA.srcs/sources_1/new/BasicModules.v | 58 ++++++++++++++++++++---- 1 file changed, 50 insertions(+), 8 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 30f1c9d..04c2750 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -168,14 +168,6 @@ module gen_clock(); endmodule -module inverter( - input wire A, - output wire B); - - assign B = ~A; - -endmodule - module mux_4_1(input wire [1:0] switch, input wire [8:0] A,B,C,D, output reg [8:0] out); @@ -191,6 +183,56 @@ module mux_4_1(input wire [1:0] switch, endmodule +module not_1bit( + input wire A, + output wire B); + + assign B = ~A; + +endmodule + +module not_9bit( + input wire [8:0] A, + output wire [8:0] B); + + not_1bit not0( + .A(A[0]) + .B(B[0])); + + not_1bit not1( + .A(A[1]) + .B(B[1])); + + not_1bit not2( + .A(A[2]) + .B(B[2])); + + not_1bit not3( + .A(A[3]) + .B(B[3])); + + not_1bit not4( + .A(A[4]) + .B(B[4])); + + not_1bit not5( + .A(A[5]) + .B(B[5])); + + not_1bit not6( + .A(A[6]) + .B(B[6])); + + not_1bit not7( + .A(A[7]) + .B(B[7])); + + not_1bit not8( + .A(A[8]) + .B(B[8])); + +endmodule + module register(input wire clk, reset, input wire [1:0] En, input wire [8:0] Din,