diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index 808c0ab..b0b58d7 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -41,19 +41,12 @@ module mux(input wire [1:0] switch,
            output reg [8:0] out);
            
     always @(A,B,C,D,switch) begin
-        if (switch == 2'b00) begin
-            out = A;
-        end
-        else if (switch == 2'b01) begin
-            out = B;
-        end
-        else if (switch == 2'b11) begin
-            out = C;
-        end
-        else begin
-            out = D;
-        end
+        case (switch)
+            2'b00 : out = A;
+            2'b01 : out = B;
+            2'b10 : out = C;
+            default: out = D;
+        endcase
     end
-
 endmodule