From ce2410e26ceda195147f6790625519fe99a23f52 Mon Sep 17 00:00:00 2001 From: "jose.rodriguezlabra" Date: Sun, 24 Mar 2019 16:04:55 -0400 Subject: [PATCH] little things --- lab2CA.cache/wt/webtalk_pa.xml | 50 +++++++++++++------------ lab2CA.srcs/sources_1/new/CPU9bits.v | 2 +- lab2CA.srcs/sources_1/new/ControlUnit.v | 2 +- 3 files changed, 29 insertions(+), 25 deletions(-) diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index dd80781..fc754a9 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -26,7 +26,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -41,28 +41,28 @@ This means code written to parse this file will need to be revisited each subseq - + - + - - + + - + - + - + @@ -71,42 +71,45 @@ This means code written to parse this file will need to be revisited each subseq - + + - - + + - + - + - + - + + + - + @@ -122,12 +125,13 @@ This means code written to parse this file will need to be revisited each subseq - + + - + @@ -153,7 +157,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -164,9 +168,9 @@ This means code written to parse this file will need to be revisited each subseq - + - +
diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index 3e04539..11ada74 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -117,7 +117,7 @@ module CPU9bits( bit1_mux_2_1 BranMux( // BEQ MUX .A(FU[0]), - .B(op0[0]), + .B(AluOut[0]), .out(fetchBranch), .switch(FU[2])); // FU[2] only goes high when BEQ diff --git a/lab2CA.srcs/sources_1/new/ControlUnit.v b/lab2CA.srcs/sources_1/new/ControlUnit.v index c9c3f7b..31ad29a 100644 --- a/lab2CA.srcs/sources_1/new/ControlUnit.v +++ b/lab2CA.srcs/sources_1/new/ControlUnit.v @@ -118,7 +118,7 @@ module ControlUnit( js <= 1'b0; end 4'b0110: begin - aluOut <= 4'b0000; + aluOut <= 4'b1010; addi <= 1'b1; // addi RegEn <= 1'b0; FU <= 3'b001; // Disable Branching