diff --git a/README.md b/README.md
index 9bb1414..98a4e60 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,10 @@
 # ECE 3570 Lab
 
-## Unknown Status of Fixes
+## Things to fix
 
-* Only two registers are being written to, first two within simulation is not being written to
\ No newline at end of file
+* Make RAM write edge-triggered only
+  * RTL_RAM is what it needs to be showing as, since VIvado will recognize it as such
+* Make ROM asyncronous (can be read at any time)
+  * RTL_ROM is what it needs to be showing as, since VIvado will recognize it as such
+* Get rid of if statememnts in RAM and ROM
+* Get programs working properly