Added outputs to the MUXes for the registers

2019-02-15 17:01:43 -05:00
parent f4c923f60c
commit d1aa8e4ffb
6 changed files with 80 additions and 21 deletions
--- a/lab2CA.srcs/sources_1/new/RegFile.v
+++ b/lab2CA.srcs/sources_1/new/RegFile.v
@@ -37,18 +37,20 @@ module RegFile(input wire clk, reset,
        .Din(write_data),
        .Dout(r3_out));    
        
-    mux m0(
+    mux_4_1 m0(
        .A(r0_out),
        .B(r1_out),
        .C(r2_out),
        .D(r3_out),
+        .out(op0),
        .switch(op0_idx));
        
-    mux m1(
+    mux_4_1 m1(
        .A(r0_out),
        .B(r1_out),
        .C(r2_out),
        .D(r3_out),
+        .out(op1),
        .switch(op1_idx));
    
 endmodule