Added outputs to the MUXes for the registers

lab2CA.srcs/sources_1/new/RegFile.v

@@ -37,18 +37,20 @@ module RegFile(input wire clk, reset,
         .Din(write_data),
         .Dout(r3_out));    
         
-    mux m0(
+    mux_4_1 m0(
         .A(r0_out),
         .B(r1_out),
         .C(r2_out),
         .D(r3_out),
+        .out(op0),
         .switch(op0_idx));
         
-    mux m1(
+    mux_4_1 m1(
         .A(r0_out),
         .B(r1_out),
         .C(r2_out),
         .D(r3_out),
+        .out(op1),
         .switch(op1_idx));
     
 endmodule