Added outputs to the MUXes for the registers
This commit is contained in:
@@ -3,7 +3,7 @@
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pa" timeStamp="Fri Feb 15 14:50:48 2019">
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<application name="pa" timeStamp="Fri Feb 15 16:48:24 2019">
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<section name="Project Information" visible="false">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="cabf4166fb474d5f964bb35d114df571" type="ProjectID"/>
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<property name="ProjectID" value="cabf4166fb474d5f964bb35d114df571" type="ProjectID"/>
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<property name="ProjectIteration" value="1" type="ProjectIteration"/>
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<property name="ProjectIteration" value="1" type="ProjectIteration"/>
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@@ -17,19 +17,54 @@ This means code written to parse this file will need to be revisited each subseq
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<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
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<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
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</item>
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</item>
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<item name="Java Command Handlers">
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<item name="Java Command Handlers">
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<property name="AddSources" value="3" type="JavaHandler"/>
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<property name="CloseProject" value="1" type="JavaHandler"/>
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<property name="EditDelete" value="1" type="JavaHandler"/>
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<property name="OpenProject" value="1" type="JavaHandler"/>
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<property name="OpenProject" value="1" type="JavaHandler"/>
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<property name="ToggleViewNavigator" value="2" type="JavaHandler"/>
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<property name="RunSchematic" value="1" type="JavaHandler"/>
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<property name="RunSynthesis" value="3" type="JavaHandler"/>
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<property name="SetTopNode" value="4" type="JavaHandler"/>
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<property name="ShowView" value="2" type="JavaHandler"/>
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8
lab2CA.runs/.jobs/vrs_config_1.xml
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8
lab2CA.runs/.jobs/vrs_config_1.xml
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@@ -0,0 +1,8 @@
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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<Parameters>
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<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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</Parameters>
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</Runs>
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8
lab2CA.runs/.jobs/vrs_config_2.xml
Normal file
8
lab2CA.runs/.jobs/vrs_config_2.xml
Normal file
@@ -0,0 +1,8 @@
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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<Parameters>
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<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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</Parameters>
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</Runs>
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8
lab2CA.runs/.jobs/vrs_config_3.xml
Normal file
8
lab2CA.runs/.jobs/vrs_config_3.xml
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@@ -0,0 +1,8 @@
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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<Parameters>
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<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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</Parameters>
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</Runs>
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@@ -37,18 +37,20 @@ module RegFile(input wire clk, reset,
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.Din(write_data),
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.Din(write_data),
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.Dout(r3_out));
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.Dout(r3_out));
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mux m0(
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mux_4_1 m0(
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.A(r0_out),
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.A(r0_out),
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.B(r1_out),
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.B(r1_out),
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.C(r2_out),
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.C(r2_out),
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.D(r3_out),
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.D(r3_out),
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.out(op0),
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.switch(op0_idx));
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.switch(op0_idx));
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mux m1(
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mux_4_1 m1(
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.A(r0_out),
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.A(r0_out),
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.B(r1_out),
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.B(r1_out),
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.C(r2_out),
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.C(r2_out),
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.D(r3_out),
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.D(r3_out),
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.out(op1),
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.switch(op1_idx));
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.switch(op1_idx));
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endmodule
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endmodule
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22
lab2CA.xpr
22
lab2CA.xpr
@@ -66,8 +66,16 @@
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<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</FileInfo>
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</File>
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</File>
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<File Path="$PSRCDIR/sources_1/new/ALU.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/new/RegFile.v">
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<File Path="$PSRCDIR/sources_1/new/RegFile.v">
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<FileInfo>
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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@@ -81,18 +89,9 @@
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<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</FileInfo>
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</File>
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</File>
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<File Path="$PSRCDIR/sources_1/new/ALU.v">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="RegFile"/>
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<Option Name="TopModule" Val="ALU"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</Config>
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</FileSet>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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@@ -105,9 +104,8 @@
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<Filter Type="Srcs"/>
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<Filter Type="Srcs"/>
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<Config>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="RegFile"/>
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<Option Name="TopModule" Val="adder_9bit"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SrcSet" Val="sources_1"/>
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<Option Name="SrcSet" Val="sources_1"/>
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