From d6cee0483c1ca81ebb15399a3675307b4845b643 Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.io>
Date: Fri, 15 Feb 2019 17:02:54 -0500
Subject: [PATCH] ALU opcode is different from instruction opcode, so reducing
 to needed operations only

---
 lab2CA.srcs/sources_1/new/ALU.v | 28 +++++++++++-----------------
 1 file changed, 11 insertions(+), 17 deletions(-)

diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v
index 4a1b181..8182a07 100644
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -1,25 +1,27 @@
 `timescale 1ns / 1ps
 
 module ALU(
-    input wire [3:0] opcode,
+    input wire [2:0] opcode,
     input wire [8:0] operand0,
     input wire [8:0] operand1,
     output wire [8:0] result 
     );
     
     // Wires for connecting the modules to the mux
-    wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P;
-    
-    // Please place modules in order of OPCODE, to make them easier to find
-    
-    
-    
-    
+    wire [8:0] A,B,C,D,E,F,G,H;
     
+    // A (000) - Add
+    // B (001) - Subtract
+    // C (010) - OR
+    // D (011) - NOR
+    // E (100) - AND
+    // F (101) - Shift Logical Left
+    // G (110) - Shift Logical Right
+    // H (111)
     
     
     // MUX chooses which result to show based on the OPCODE
-    mux_16_1 mux_result(
+    mux_8_1 mux_result(
         .switch(opcode),
         .A(A),
         .B(B),
@@ -29,14 +31,6 @@ module ALU(
         .F(F),
         .G(G),
         .H(H),
-        .I(I),
-        .J(J),
-        .K(K),
-        .L(L),
-        .M(M),
-        .N(N),
-        .O(O),
-        .P(P),
         .out(result));
 
 endmodule