From d8c7031e1b49e1205f46d353603da9a8d262263b Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.me>
Date: Fri, 29 Mar 2019 17:21:29 -0400
Subject: [PATCH] Fixed unconnected wires

---
 lab2CA.srcs/sources_1/new/ALU.v | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v
index 2c018c9..281ce37 100644
--- a/lab2CA.srcs/sources_1/new/ALU.v
+++ b/lab2CA.srcs/sources_1/new/ALU.v
@@ -10,8 +10,8 @@ module ALU(
     // Wires for connecting the modules to the mux
     wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H,result_I,result_J,result_K,result_L,result_M,result_N,result_O,result_P;
     wire cout;
-    // A (0000) - Add
-    
+
+    // A (0000) - Add    
     add_9bit add0(
         .A(operand0),
         .B(operand1),
@@ -41,15 +41,15 @@ module ALU(
         .C(result_E));
     // F (0101) - Shift Left
     shift_left sl(
-        .A(operand0),
+        .A(operand0[7:0]),
         .B(result_F));
     // G (0110) - Shift Right Logical
     shift_right_logical srl(
-        .A(operand0),
+        .A(operand0[8:1]),
         .B(result_G));
     // H (0111) - Shift Right Arithmetic
     shift_right_arithmetic sra(
-        .A(operand0),
+        .A(operand0[8:1]),
         .B(result_H));
     // I (1000) - NOT
     not_9bit not0(