diff --git a/README.md b/README.md index d4c4a24..9bb1414 100644 --- a/README.md +++ b/README.md @@ -1,17 +1,5 @@ # ECE 3570 Lab -## Fixes To Be Implemented +## Unknown Status of Fixes -* Get rid of the double zero for the enable on the registers - * Make decoder for it -* Redo simulations with other registers using internal signals -* Fix simulation waveforms for Registers, as we are currently changing inputs too quickly (multiple times within a clock cycle) -* Only two registers are being written to, first two within simulation is not being written to -* Need to allow for signed numbers -* Remove subtraction from ALU -* Have arithmetic shift left and right -* Uncomment all testbenches (We can have multiple testbenches active at once) -* Bitwise operations do not need a 1-bit implementation, modify 9-bit and keep it only -* Comparator needed -* Make subtraction more efficient -* Need to verify that FetchUnit is working properly as Martin had some concerns that it probably wasn't functioning properly \ No newline at end of file +* Only two registers are being written to, first two within simulation is not being written to \ No newline at end of file