From dd7a319e928b7d006e026ed2c1463ad231e385d0 Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.me>
Date: Sat, 6 Apr 2019 16:08:02 -0400
Subject: [PATCH] Better indentation

---
 lab2CA.srcs/sources_1/new/FetchUnit.v | 11 ++++++-----
 lab2CA.srcs/sources_1/new/RegFile.v   | 10 ++++++----
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v
index 3e77260..17440c3 100644
--- a/lab2CA.srcs/sources_1/new/FetchUnit.v
+++ b/lab2CA.srcs/sources_1/new/FetchUnit.v
@@ -1,9 +1,11 @@
 `timescale 1ns / 1ps
 
-module FetchUnit(input wire clk, reset, 
-                 input wire op_idx,
-                 input wire [8:0] AddrIn,
-                 output wire [8:0] AddrOut);
+module FetchUnit(
+    input wire clk, reset, 
+    input wire op_idx,
+    input wire [8:0] AddrIn,
+    output wire [8:0] AddrOut
+        );
   
     //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) 
     wire [8:0] progC_out, result_m;
@@ -29,7 +31,6 @@ module FetchUnit(input wire clk, reset,
         .out(result_m),
         .switch(op_idx));
         
-        
 endmodule
 
 //testbench
diff --git a/lab2CA.srcs/sources_1/new/RegFile.v b/lab2CA.srcs/sources_1/new/RegFile.v
index de3ea8e..3a4e24c 100644
--- a/lab2CA.srcs/sources_1/new/RegFile.v
+++ b/lab2CA.srcs/sources_1/new/RegFile.v
@@ -1,9 +1,11 @@
 `timescale 1ns / 1ps
 
-module RegFile(input wire clk, reset, enable,
-                input wire [1:0] write_index, op0_idx, op1_idx,
-                input wire [8:0] write_data,
-                output wire [8:0] op0, op1);
+module RegFile(
+    input wire clk, reset, enable,
+    input wire [1:0] write_index, op0_idx, op1_idx,
+    input wire [8:0] write_data,
+    output wire [8:0] op0, op1
+    );
     
     wire [3:0] decOut;
     wire [8:0] r0_out, r1_out, r2_out, r3_out;