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Tweaked forwarding check. Program 3 works with a few stalls

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This commit is contained in:
jose.rodriguezlabra
2019-04-12 00:01:27 -04:00
parent 0118debfb9
commit ddf47c7eee
13 changed files with 356 additions and 258 deletions
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4
lab2CA.srcs/sources_1/new/BasicModules.v
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@@ -850,8 +850,8 @@ module fDPipReg(
input wire clk,
input wire reset,
input wire En,
input wire [50:0] Din,
output reg [50:0] Dout);
input wire [52:0] Din,
output reg [52:0] Dout);
always @(posedge clk) begin
if (reset == 1'b1) begin

37
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -9,7 +9,8 @@ module CPU9bits(
wire [8:0] RFIn,FUAddr, op0_ext, op1_ext, wr_ext, op0_sub, op1_sub, op0_zero, op1_zero, op0_and, op1_and, newOp0, newOp1;
wire [1:0] instr, op0_idx, op1_idx;
wire fetchBranch, RegEn, compare0, compare1;
wire [50:0] FDOut, FDPipOut, EMIn;
wire [50:0] EMIn;
wire [52:0] FDOut,FDPipOut;
wire [61:0] EMOut, EMPipOut;
@@ -25,26 +26,26 @@ module CPU9bits(
.RFIn(RFIn),
.AddrIn(FUAddr),
.RFIdx(instr),
.result(FDOut),
.done(done),
.compare0(compare0),
.compare1(compare1),
.op0_idx(op0_idx),
.op1_idx(op1_idx)
.result(FDOut), ////////////////////
.done(done)
//.compare0(compare0),
//.compare1(compare1),
//.op0_idx(op0_idx),
//.op1_idx(op1_idx)
);
fDPipReg pipe1(
.clk(clk),
.reset(reset),
.En(1'b0),
.Din(FDOut),
.Dout(FDPipOut)
.Din(FDOut), ///////////////////
.Dout(FDPipOut)///////////////////
);
EMModule EM(
.reset(reset),
.clk(clk),
.PipIn(EMIn),
.PipIn(EMIn),/////////////////
.PipOut(EMOut)
);
@@ -66,12 +67,12 @@ module CPU9bits(
);
sign_extend_2bit ext0(
.A(op0_idx),
.A(FDPipOut[46:45]),
.B(op0_ext)
);
sign_extend_2bit ext1(
.A(op1_idx),
.A(FDPipOut[44:43]),
.B(op1_ext)
);
@@ -104,26 +105,28 @@ module CPU9bits(
and_9bit and0(
.A(~op0_zero),
.B({8'b00000000,compare0}),
.B({8'b00000000,FDPipOut[52]}),
.C(op0_and)
);
and_9bit and1(
.A(~op1_zero),
.B({8'b00000000,compare1}),
.B({8'b00000000,FDPipOut[51]}),
.C(op1_and)
);
mux_2_1 mux0(
.switch(op0_and[0]),
.A(FDOut[41:33]),
//.switch(1'b0),
.A(FDPipOut[41:33]),
.B(EMPipOut[33:25]), //ALUOut
.out(newOp0)
);
mux_2_1 mux1(
.switch(op1_and[0]),
.A(FDOut[32:24]),
//.switch(1'b0),
.A(FDPipOut[32:24]),
.B(EMPipOut[33:25]), //ALUOut
.out(newOp1)
);
@@ -154,7 +157,7 @@ module CPU9bits_tb();
reset = 1'b1;
#10
reset = 1'b0;
#300
#200
$finish;
end

12
lab2CA.srcs/sources_1/new/FDModule.v
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@@ -4,9 +4,9 @@ module FDModule(
input wire reset, clk, FUIdx, En,
input wire [8:0] RFIn, AddrIn,
input wire[1:0] RFIdx,
output wire [1:0] op0_idx, op1_idx,
output wire [50:0] result,
output wire done, compare0, compare1
//output wire [1:0] op0_idx, op1_idx,
output wire [52:0] result,
output wire done//, compare0, compare1
);
@@ -16,9 +16,9 @@ module FDModule(
wire [1:0] bankS;
wire addiS, RegEn, loadS, halt, link, js, dataMemEn ;
assign result = {instr,op0,op1,PCout,addiS,RegEn,loadS,link,js,dataMemEn,aluOp,FU,bankS}; // concat all signals into one
assign op0_idx = instr[4:3];
assign op1_idx = instr[2:1];
assign result = {compare0,compare1,instr,op0,op1,PCout,addiS,RegEn,loadS,link,js,dataMemEn,aluOp,FU,bankS}; // concat all signals into one
//assign op0_idx = instr[4:3];46-45
//assign op1_idx = instr[2:1];44-43
instructionMemory iM(

202
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -97,107 +97,107 @@ module dataMemory(
// Program 1 Test Data
memory[0] <= 9'd100;
memory[1] <= 9'd58;
memory[2] <= 9'd6;
memory[3] <= 9'd12;
memory[4] <= 9'b110110000; // -80
memory[5] <= 9'd17;
memory[6] <= 9'b111011011; // -37
memory[7] <= 9'd25;
memory[8] <= -9'd83; // -83
memory[9] <= -9'd98; // -98
memory[10] <= -9'd98; // -98
memory[11] <= -9'd74; // -74
memory[12] <= 9'd70;
memory[13] <= -9'd38; // -38
memory[14] <= 9'd52;
memory[15] <= -9'd96; // -96
memory[16] <= -9'd32; // -32
memory[17] <= -9'd93; // -93
memory[18] <= -9'd40; // -40
memory[19] <= 9'd59;
memory[20] <= 9'd10;
memory[21] <= 9'd81;
memory[22] <= -9'd23; // -28
memory[23] <=- 9'd99; // -99
memory[24] <= -9'd41; // -41
memory[25] <= 9'd33;
memory[26] <= 9'd98;
memory[27] <= 9'd73;
memory[28] <= -9'd1; // -1
memory[29] <= 9'd28;
memory[30] <= 9'd5;
memory[31] <= -9'd74; // -74
memory[32] <= -9'd41; // -41
memory[33] <= 9'd41;
memory[34] <= 9'd39;
memory[35] <= 9'd62;
memory[36] <= 9'd19;
memory[37] <= -9'd40; // -40
memory[38] <= -9'd8; // -8
memory[39] <= 9'd92;
memory[40] <= 9'd37;
memory[41] <= 9'd50;
memory[42] <= -9'd72; // -72
memory[43] <= -9'd5; // -5
memory[44] <= 9'd19;
memory[45] <= 9'd58;
memory[46] <= -9'd13; // -13
memory[47] <= 9'd0;
memory[48] <= -9'd97; // -97
memory[49] <= 9'd54;
memory[50] <= -9'd17; // -17
memory[51] <= -9'd83; // -83
memory[52] <= 9'd53;
memory[53] <= 9'd82;
memory[54] <= -9'd94; // -94
memory[55] <= -9'd77; // -77
memory[56] <= -9'd74; // -74
memory[57] <= -9'd52; // -52
memory[58] <= 9'd85;
memory[59] <= -9'd65; // -65
memory[60] <= -9'd10; // -10
memory[61] <= -9'd45; // -45
memory[62] <= -9'd92; // -92
memory[63] <= -9'd30; // -30
memory[64] <= 9'd18;
memory[65] <= -9'd95; // -95
memory[66] <= -9'd27; // -27
memory[67] <= -9'd74; // -74
memory[68] <= 9'd62;
memory[69] <= 9'd64;
memory[70] <= -9'd9; // -9
memory[71] <= 9'd66;
memory[72] <= -9'd71; // -71
memory[73] <= -9'd31; // -31
memory[74] <= 9'd34;
memory[75] <= 9'd12;
memory[76] <= 9'd3;
memory[77] <= 9'd82;
memory[78] <= 9'd13;
memory[79] <= -9'd78; // -78
memory[80] <= -9'd8; // -8
memory[81] <= 9'd88;
memory[82] <= 9'd42;
memory[83] <= 9'd42;
memory[84] <= 9'd21;
memory[85] <= -9'd44; // -44
memory[86] <= 9'd30;
memory[87] <= -9'd93; // -93
memory[88] <= 9'd2;
memory[89] <= -9'd34; // -34
memory[90] <= 9'd92;
memory[91] <= -9'd45; // -45
memory[92] <= 9'd26;
memory[93] <= -9'd79; // -79
memory[94] <= 9'd43;
memory[95] <= -9'd25; // -25
memory[96] <= -9'd24; // -24
memory[97] <= -9'd25; // -25
memory[98] <= -9'd19; // -19
memory[99] <= -9'd49; // -49
memory[100] <= -9'd8; // -8
// memory[0] <= 9'd100;
// memory[1] <= 9'd58;
// memory[2] <= 9'd6;
// memory[3] <= 9'd12;
// memory[4] <= 9'b110110000; // -80
// memory[5] <= 9'd17;
// memory[6] <= 9'b111011011; // -37
// memory[7] <= 9'd25;
// memory[8] <= -9'd83; // -83
// memory[9] <= -9'd98; // -98
// memory[10] <= -9'd98; // -98
// memory[11] <= -9'd74; // -74
// memory[12] <= 9'd70;
// memory[13] <= -9'd38; // -38
// memory[14] <= 9'd52;
// memory[15] <= -9'd96; // -96
// memory[16] <= -9'd32; // -32
// memory[17] <= -9'd93; // -93
// memory[18] <= -9'd40; // -40
// memory[19] <= 9'd59;
// memory[20] <= 9'd10;
// memory[21] <= 9'd81;
// memory[22] <= -9'd23; // -28
// memory[23] <=- 9'd99; // -99
// memory[24] <= -9'd41; // -41
// memory[25] <= 9'd33;
// memory[26] <= 9'd98;
// memory[27] <= 9'd73;
// memory[28] <= -9'd1; // -1
// memory[29] <= 9'd28;
// memory[30] <= 9'd5;
// memory[31] <= -9'd74; // -74
// memory[32] <= -9'd41; // -41
// memory[33] <= 9'd41;
// memory[34] <= 9'd39;
// memory[35] <= 9'd62;
// memory[36] <= 9'd19;
// memory[37] <= -9'd40; // -40
// memory[38] <= -9'd8; // -8
// memory[39] <= 9'd92;
// memory[40] <= 9'd37;
// memory[41] <= 9'd50;
// memory[42] <= -9'd72; // -72
// memory[43] <= -9'd5; // -5
// memory[44] <= 9'd19;
// memory[45] <= 9'd58;
// memory[46] <= -9'd13; // -13
// memory[47] <= 9'd0;
// memory[48] <= -9'd97; // -97
// memory[49] <= 9'd54;
// memory[50] <= -9'd17; // -17
// memory[51] <= -9'd83; // -83
// memory[52] <= 9'd53;
// memory[53] <= 9'd82;
// memory[54] <= -9'd94; // -94
// memory[55] <= -9'd77; // -77
// memory[56] <= -9'd74; // -74
// memory[57] <= -9'd52; // -52
// memory[58] <= 9'd85;
// memory[59] <= -9'd65; // -65
// memory[60] <= -9'd10; // -10
// memory[61] <= -9'd45; // -45
// memory[62] <= -9'd92; // -92
// memory[63] <= -9'd30; // -30
// memory[64] <= 9'd18;
// memory[65] <= -9'd95; // -95
// memory[66] <= -9'd27; // -27
// memory[67] <= -9'd74; // -74
// memory[68] <= 9'd62;
// memory[69] <= 9'd64;
// memory[70] <= -9'd9; // -9
// memory[71] <= 9'd66;
// memory[72] <= -9'd71; // -71
// memory[73] <= -9'd31; // -31
// memory[74] <= 9'd34;
// memory[75] <= 9'd12;
// memory[76] <= 9'd3;
// memory[77] <= 9'd82;
// memory[78] <= 9'd13;
// memory[79] <= -9'd78; // -78
// memory[80] <= -9'd8; // -8
// memory[81] <= 9'd88;
// memory[82] <= 9'd42;
// memory[83] <= 9'd42;
// memory[84] <= 9'd21;
// memory[85] <= -9'd44; // -44
// memory[86] <= 9'd30;
// memory[87] <= -9'd93; // -93
// memory[88] <= 9'd2;
// memory[89] <= -9'd34; // -34
// memory[90] <= 9'd92;
// memory[91] <= -9'd45; // -45
// memory[92] <= 9'd26;
// memory[93] <= -9'd79; // -79
// memory[94] <= 9'd43;
// memory[95] <= -9'd25; // -25
// memory[96] <= -9'd24; // -24
// memory[97] <= -9'd25; // -25
// memory[98] <= -9'd19; // -19
// memory[99] <= -9'd49; // -49
// memory[100] <= -9'd8; // -8

21
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -5,7 +5,7 @@ module instructionMemory(
output reg [8:0] readData
);
reg [8:0] memory [8:0]; // Maximum of 512 memory locations
reg [8:0] memory [18:0]; // Maximum of 512 memory locations
// Vivado will give warnings of unconnected ports on the "address" bus if they are unused
initial begin
@@ -13,12 +13,19 @@ module instructionMemory(
memory[0] <= 9'b000000000; //Stall
memory[1] <= 9'b000000000; //Stall
memory[2] <= 9'b011000000; //addi
memory[3] <= 9'b011001001; //addi
memory[4] <= 9'b000100000; //load
memory[5] <= 9'b000101010; //load
memory[6] <= 9'b010100010; //add
memory[7] <= 9'b111100000; //shift left
memory[8] <= 9'b111100000; //shift left
memory[3] <= 9'b000000000; //Stall
memory[4] <= 9'b000000000; //Stall
memory[5] <= 9'b011001001; //addi
memory[6] <= 9'b000000000; //Stall
memory[7] <= 9'b000000000; //Stall
memory[8] <= 9'b000100000; //load
memory[9] <= 9'b000000000; //Stall
memory[10] <= 9'b000101010; //load
memory[11] <= 9'b010100010; //add
memory[12] <= 9'b111100000; //shift left
memory[13] <= 9'b111100000; //shift left
memory[14] <= 9'b000000000; //Stall
memory[15] <= 9'b000000000; //Stall
// //Testing all instructions
// memory[6] <= 9'b010100011; //sub