Tweaked forwarding check. Program 3 works with a few stalls

2019-04-12 00:01:27 -04:00
parent 0118debfb9
commit ddf47c7eee
13 changed files with 356 additions and 258 deletions
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -850,8 +850,8 @@ module fDPipReg(
        input wire clk, 
 	    input wire reset, 
 	    input wire En, 
-	    input wire [50:0] Din, 
-	    output reg [50:0] Dout);
+	    input wire [52:0] Din, 
+	    output reg [52:0] Dout);
 	    
 	    always @(posedge clk) begin
 		if (reset == 1'b1) begin