Tweaked forwarding check. Program 3 works with a few stalls

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -9,7 +9,8 @@ module CPU9bits(
     wire [8:0] RFIn,FUAddr, op0_ext, op1_ext, wr_ext, op0_sub, op1_sub, op0_zero, op1_zero, op0_and, op1_and, newOp0, newOp1;
     wire [1:0] instr, op0_idx, op1_idx;
     wire fetchBranch, RegEn, compare0, compare1;
-    wire [50:0] FDOut, FDPipOut, EMIn;
+    wire [50:0] EMIn;
+    wire [52:0] FDOut,FDPipOut;
     wire [61:0] EMOut, EMPipOut;
     
     
@@ -25,26 +26,26 @@ module CPU9bits(
         .RFIn(RFIn),
         .AddrIn(FUAddr), 
         .RFIdx(instr),
-        .result(FDOut),
-        .done(done),
-        .compare0(compare0),
-        .compare1(compare1),
-        .op0_idx(op0_idx),
-        .op1_idx(op1_idx)
+        .result(FDOut), ////////////////////
+        .done(done)
+        //.compare0(compare0),
+        //.compare1(compare1),
+        //.op0_idx(op0_idx),
+        //.op1_idx(op1_idx)
      );
      
      fDPipReg pipe1(
         .clk(clk), 
 	    .reset(reset), 
 	    .En(1'b0), 
-	    .Din(FDOut), 
-	    .Dout(FDPipOut)
+	    .Din(FDOut), ///////////////////
+	    .Dout(FDPipOut)///////////////////
 	 );
         
      EMModule EM(
         .reset(reset),
         .clk(clk),
-        .PipIn(EMIn),
+        .PipIn(EMIn),/////////////////
         .PipOut(EMOut)
      );
     
@@ -66,12 +67,12 @@ module CPU9bits(
      );
      
      sign_extend_2bit ext0(
-     .A(op0_idx),
+     .A(FDPipOut[46:45]),
      .B(op0_ext)
      );
      
      sign_extend_2bit ext1(
-     .A(op1_idx),
+     .A(FDPipOut[44:43]),
      .B(op1_ext)
      );
      
@@ -104,26 +105,28 @@ module CPU9bits(
      
      and_9bit and0(
      .A(~op0_zero),
-     .B({8'b00000000,compare0}),
+     .B({8'b00000000,FDPipOut[52]}),
      .C(op0_and)
      );
      
      and_9bit and1(
      .A(~op1_zero),
-     .B({8'b00000000,compare1}),
+     .B({8'b00000000,FDPipOut[51]}),
      .C(op1_and)
      );
      
      mux_2_1 mux0(
      .switch(op0_and[0]),
-     .A(FDOut[41:33]),
+     //.switch(1'b0),
+     .A(FDPipOut[41:33]),
      .B(EMPipOut[33:25]), //ALUOut
      .out(newOp0)
      );
      
      mux_2_1 mux1(
      .switch(op1_and[0]),
-     .A(FDOut[32:24]),
+     //.switch(1'b0),
+     .A(FDPipOut[32:24]),
      .B(EMPipOut[33:25]), //ALUOut
      .out(newOp1)
      );
@@ -154,7 +157,7 @@ module CPU9bits_tb();
     	reset = 1'b1;
     	#10
     	reset = 1'b0;
-    	#300
+    	#200
         $finish;
         
     end