Tweaked forwarding check. Program 3 works with a few stalls

lab2CA.srcs/sources_1/new/FDModule.v

@@ -4,9 +4,9 @@ module FDModule(
         input wire reset, clk, FUIdx, En,
         input wire [8:0] RFIn, AddrIn, 
         input wire[1:0] RFIdx,
-        output wire [1:0] op0_idx, op1_idx,
-        output wire [50:0] result,
-        output wire done, compare0, compare1
+        //output wire [1:0] op0_idx, op1_idx,
+        output wire [52:0] result,
+        output wire done//, compare0, compare1
         );
         
         
@@ -16,9 +16,9 @@ module FDModule(
         wire [1:0] bankS;
         wire addiS, RegEn, loadS, halt, link, js, dataMemEn ;
        
-        assign result = {instr,op0,op1,PCout,addiS,RegEn,loadS,link,js,dataMemEn,aluOp,FU,bankS};   // concat all signals into one
-        assign op0_idx = instr[4:3];
-        assign op1_idx = instr[2:1];
+        assign result = {compare0,compare1,instr,op0,op1,PCout,addiS,RegEn,loadS,link,js,dataMemEn,aluOp,FU,bankS};   // concat all signals into one
+        //assign op0_idx = instr[4:3];46-45
+        //assign op1_idx = instr[2:1];44-43
 
         
     instructionMemory iM(