diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 652ae82..391e24d 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -27,17 +27,18 @@ This means code written to parse this file will need to be revisited each subseq - + - + - - + + + @@ -48,7 +49,8 @@ This means code written to parse this file will need to be revisited each subseq - + + @@ -58,18 +60,18 @@ This means code written to parse this file will need to be revisited each subseq - - + + - + - + @@ -88,12 +90,12 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -118,7 +120,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -129,9 +131,10 @@ This means code written to parse this file will need to be revisited each subseq - + + - + @@ -141,10 +144,10 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -162,7 +165,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -172,29 +175,33 @@ This means code written to parse this file will need to be revisited each subseq - - + + + + + - + - + + - + - +
diff --git a/lab2CA.runs/.jobs/vrs_config_58.xml b/lab2CA.runs/.jobs/vrs_config_58.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_58.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_59.xml b/lab2CA.runs/.jobs/vrs_config_59.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_59.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_60.xml b/lab2CA.runs/.jobs/vrs_config_60.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_60.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_61.xml b/lab2CA.runs/.jobs/vrs_config_61.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_61.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_62.xml b/lab2CA.runs/.jobs/vrs_config_62.xml new file mode 100644 index 0000000..c86769b --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_62.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/impl_1/CPU9bits.tcl b/lab2CA.runs/impl_1/CPU9bits.tcl deleted file mode 100644 index 8e1b126..0000000 --- a/lab2CA.runs/impl_1/CPU9bits.tcl +++ /dev/null @@ -1,152 +0,0 @@ -# -# Report generation script generated by Vivado -# - -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -proc start_step { step } { - set stopFile ".stop.rst" - if {[file isfile .stop.rst]} { - puts "" - puts "*** Halting run - EA reset detected ***" - puts "" - puts "" - return -code error - } - set beginFile ".$step.begin.rst" - set platform "$::tcl_platform(platform)" - set user "$::tcl_platform(user)" - set pid [pid] - set host "" - if { [string equal $platform unix] } { - if { [info exist ::env(HOSTNAME)] } { - set host $::env(HOSTNAME) - } - } else { - if { [info exist ::env(COMPUTERNAME)] } { - set host $::env(COMPUTERNAME) - } - } - set ch [open $beginFile w] - puts $ch "" - puts $ch "" - puts $ch " " - puts $ch " " - puts $ch "" - close $ch -} - -proc end_step { step } { - set endFile ".$step.end.rst" - set ch [open $endFile w] - close $ch -} - -proc step_failed { step } { - set endFile ".$step.error.rst" - set ch [open $endFile w] - close $ch -} - -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 - -start_step init_design -set ACTIVE_STEP init_design -set rc [catch { - create_msg_db init_design.pb - create_project -in_memory -part xc7k160tifbg484-2L - set_property design_mode GateLvl [current_fileset] - set_param project.singleFileAddWarning.threshold 0 - set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project] - set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project] - set_property ip_output_repo {{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip}} [current_project] - set_property ip_cache_permissions {read write} [current_project] - add_files -quiet {{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp}} - link_design -top CPU9bits -part xc7k160tifbg484-2L - close_msg_db -file init_design.pb -} RESULT] -if {$rc} { - step_failed init_design - return -code error $RESULT -} else { - end_step init_design - unset ACTIVE_STEP -} - -start_step opt_design -set ACTIVE_STEP opt_design -set rc [catch { - create_msg_db opt_design.pb - opt_design - write_checkpoint -force CPU9bits_opt.dcp - create_report "impl_1_opt_report_drc_0" "report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx" - close_msg_db -file opt_design.pb -} RESULT] -if {$rc} { - step_failed opt_design - return -code error $RESULT -} else { - end_step opt_design - unset ACTIVE_STEP -} - -start_step place_design -set ACTIVE_STEP place_design -set rc [catch { - create_msg_db place_design.pb - if { [llength [get_debug_cores -quiet] ] > 0 } { - implement_debug_core - } - place_design - write_checkpoint -force CPU9bits_placed.dcp - create_report "impl_1_place_report_io_0" "report_io -file CPU9bits_io_placed.rpt" - create_report "impl_1_place_report_utilization_0" "report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb" - create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt" - close_msg_db -file place_design.pb -} RESULT] -if {$rc} { - step_failed place_design - return -code error $RESULT -} else { - end_step place_design - unset ACTIVE_STEP -} - -start_step route_design -set ACTIVE_STEP route_design -set rc [catch { - create_msg_db route_design.pb - route_design - write_checkpoint -force CPU9bits_routed.dcp - create_report "impl_1_route_report_drc_0" "report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx" - create_report "impl_1_route_report_methodology_0" "report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx" - create_report "impl_1_route_report_power_0" "report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx" - create_report "impl_1_route_report_route_status_0" "report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb" - create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation " - create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt" - create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt" - create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx" - close_msg_db -file route_design.pb -} RESULT] -if {$rc} { - write_checkpoint -force CPU9bits_routed_error.dcp - step_failed route_design - return -code error $RESULT -} else { - end_step route_design - unset ACTIVE_STEP -} - diff --git a/lab2CA.runs/impl_1/CPU9bits.vdi b/lab2CA.runs/impl_1/CPU9bits.vdi deleted file mode 100644 index 492611e..0000000 --- a/lab2CA.runs/impl_1/CPU9bits.vdi +++ /dev/null @@ -1,473 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 30 15:53:31 2019 -# Process ID: 13696 -# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1 -# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace -# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi -# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source CPU9bits.tcl -notrace -Command: link_design -top CPU9bits -part xc7k160tifbg484-2L -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7k160tifbg484-2L -INFO: [Project 1-570] Preparing netlist for logic optimization -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 581.816 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 587.391 ; gain = 332.746 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 603.059 ; gain = 15.668 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1127.293 ; gain = 524.234 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.196 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.199 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1225.961 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.206 . Memory (MB): peak = 1225.961 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -INFO: [Pwropt 34-9] Applying IDT optimizations ... -INFO: [Pwropt 34-10] Applying ODC optimizations ... -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.000 | TNS=0.000 | -WARNING: [Power 33-232] No user defined clocks were found in the design! -Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation - - -Starting PowerOpt Patch Enables Task -INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. -INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports -Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2 -Ending PowerOpt Patch Enables Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Ending Power Optimization Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1335.719 ; gain = 109.758 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 257e1e38 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1335.719 ; gain = 748.328 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx -Command: report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt. -report_drc completed successfully -report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e0025bd - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: be8e8081 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 154227d99 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 154227d99 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 154227d99 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 2 Global Placement - -Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 154227d99 - -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 -WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer -Phase 2 Global Placement | Checksum: 168f30526 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3 Detail Placement - -Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 168f30526 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10b26ca05 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 171e1f517 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 171e1f517 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 4 Post Placement Optimization and Clean-Up - -Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 - -Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: eb242549 - -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: eb242549 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Ending Placer Task | Checksum: 99ceed10 - -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -45 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. -place_design completed successfully -place_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.323 . Memory (MB): peak = 1335.719 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.130 . Memory (MB): peak = 1335.719 ; gain = 0.000 -INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb -INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Command: route_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' -Running DRC as a precondition to command route_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - - -Starting Routing Task -INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 7bcec753 ConstDB: 0 ShapeSum: 1e0025bd RouteDB: 0 - -Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 16c615449 - -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1486.191 ; gain = 150.473 -Post Restoration Checksum: NetGraph: 8cbcc684 NumContArr: dfa48dc5 Constraints: 0 Timing: 0 - -Phase 2 Router Initialization -INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. - -Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 16c615449 - -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1490.352 ; gain = 154.633 - -Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 16c615449 - -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1490.352 ; gain = 154.633 - Number of Nodes with overlaps = 0 -Phase 2 Router Initialization | Checksum: 10053be5d - -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 94ab7af4 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 4 Rip-up And Reroute - -Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 15 - Number of Nodes with overlaps = 0 -Phase 4.1 Global Iteration 0 | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 -Phase 4 Rip-up And Reroute | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 6 Post Hold Fix - -Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 -Phase 6 Post Hold Fix | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 7 Route finalize - -Router Utilization Summary - Global Vertical Routing Utilization = 0.00626714 % - Global Horizontal Routing Utilization = 0.0102302 % - Routable Net Status* - *Does not include unroutable nets such as driverless and loadless. - Run report_route_status for detailed report. - Number of Failed Nets = 0 - Number of Unrouted Nets = 0 - Number of Partially Routed Nets = 0 - Number of Node Overlaps = 0 - -Congestion Report -North Dir 1x1 Area, Max Cong = 18.9189%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 10.8108%, No Congested Regions. -East Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions. -West Dir 1x1 Area, Max Cong = 27.9412%, No Congested Regions. - ------------------------------- -Reporting congestion hotspots ------------------------------- -Direction: North ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: South ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: East ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Direction: West ----------------- -Congested clusters found at Level 0 -Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 - -Phase 7 Route finalize | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 8 Verifying routed nets - - Verification completed successfully -Phase 8 Verifying routed nets | Checksum: ab64b9a3 - -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 148b7f565 - -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 -INFO: [Route 35-16] Router Completed Successfully - -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 - -Routing Is Done. -INFO: [Common 17-83] Releasing license: Implementation -57 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. -route_design completed successfully -route_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:42 . Memory (MB): peak = 1517.723 ; gain = 182.004 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1517.723 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -Writing placer database... -Writing XDEF routing. -Writing XDEF routing logical nets. -Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1517.723 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx -Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx -INFO: [IP_Flow 19-1839] IP Catalog is up to date. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt. -report_drc completed successfully -INFO: [runtcl-4] Executing : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx -Command: report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx -INFO: [Timing 38-35] Done setting XDC timing constraints. -INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt. -report_methodology completed successfully -INFO: [runtcl-4] Executing : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx -Command: report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx -WARNING: [Power 33-232] No user defined clocks were found in the design! -Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate -INFO: [Timing 38-35] Done setting XDC timing constraints. -Running Vector-less Activity Propagation... - -Finished Running Vector-less Activity Propagation -68 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. -report_power completed successfully -INFO: [runtcl-4] Executing : report_route_status -file CPU9bits_route_status.rpt -pb CPU9bits_route_status.pb -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. -INFO: [runtcl-4] Executing : report_incremental_reuse -file CPU9bits_incremental_reuse_routed.rpt -INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. -INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt -INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Sat Mar 30 15:55:20 2019... diff --git a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb deleted file mode 100644 index 3390588..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt deleted file mode 100644 index dad6504..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt +++ /dev/null @@ -1,15 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:20 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx -| Design : CPU9bits -| Device : 7k160ti-fbg484 -| Speed File : -2L PRODUCTION 1.12 2017-02-17 ---------------------------------------------------------------------------------------------------------------------------------------------------------- - -Bus Skew Report - -No bus skew constraints - diff --git a/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt deleted file mode 100644 index be7e934..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt +++ /dev/null @@ -1,154 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:20 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt -| Design : CPU9bits -| Device : 7k160ti-fbg484 -| Speed File : -2L PRODUCTION 1.12 2017-02-17 -| Temperature Grade : I -------------------------------------------------------------------------------------------- - -Clock Utilization Report - -Table of Contents ------------------ -1. Clock Primitive Utilization -2. Global Clock Resources -3. Global Clock Source Details -4. Clock Regions: Key Resource Utilization -5. Clock Regions : Global Clock Summary -6. Device Cell Placement Summary for Global Clock g0 -7. Clock Region Cell Placement per Global Clock: Region X0Y1 - -1. Clock Primitive Utilization ------------------------------- - -+----------+------+-----------+-----+--------------+--------+ -| Type | Used | Available | LOC | Clock Region | Pblock | -+----------+------+-----------+-----+--------------+--------+ -| BUFGCTRL | 1 | 32 | 0 | 0 | 0 | -| BUFH | 0 | 120 | 0 | 0 | 0 | -| BUFIO | 0 | 32 | 0 | 0 | 0 | -| BUFMR | 0 | 16 | 0 | 0 | 0 | -| BUFR | 0 | 32 | 0 | 0 | 0 | -| MMCM | 0 | 8 | 0 | 0 | 0 | -| PLL | 0 | 8 | 0 | 0 | 0 | -+----------+------+-----------+-----+--------------+--------+ - - -2. Global Clock Resources -------------------------- - -+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 22 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | -+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) - - -3. Global Clock Source Details ------------------------------- - -+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | -+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -| src0 | g0 | IBUF/O | None | IOB_X0Y78 | X0Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | -+-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) - - -4. Clock Regions: Key Resource Utilization ------------------------------------------- - -+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ -| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | -| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 21 | 2800 | 14 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | -| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | -| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 | -| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | -+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -* Global Clock column represents track count; while other columns represents cell counts - - -5. Clock Regions : Global Clock Summary ---------------------------------------- - -All Modules -+----+----+----+ -| | X0 | X1 | -+----+----+----+ -| Y4 | 0 | 0 | -| Y3 | 0 | 0 | -| Y2 | 0 | 0 | -| Y1 | 1 | 0 | -| Y0 | 0 | 0 | -+----+----+----+ - - -6. Device Cell Placement Summary for Global Clock g0 ----------------------------------------------------- - -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -| g0 | BUFG/O | n/a | | | | 22 | 0 | 0 | 0 | clk_IBUF_BUFG | -+-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -* Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources -** IO Loads column represents load cell count of IO types -*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) -**** GT Loads column represents load cell count of GT types - - -+----+-----+----+ -| | X0 | X1 | -+----+-----+----+ -| Y4 | 0 | 0 | -| Y3 | 0 | 0 | -| Y2 | 0 | 0 | -| Y1 | 22 | 0 | -| Y0 | 0 | 0 | -+----+-----+----+ - - -7. Clock Region Cell Placement per Global Clock: Region X0Y1 ------------------------------------------------------------- - -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ -| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ -| g0 | n/a | BUFG/O | None | 22 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | -+-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ -* Clock Loads column represents the clock pin loads (pin count) -** Non-Clock Loads column represents the non-clock pin loads (pin count) -*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts - - - -# Location of BUFG Primitives -set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] - -# Location of IO Primitives which is load of clock spine - -# Location of clock ports -set_property LOC IOB_X0Y78 [get_ports clk] - -# Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" -#startgroup -create_pblock {CLKAG_clk_IBUF_BUFG} -add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] -resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} -#endgroup diff --git a/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt deleted file mode 100644 index b20d0aa..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt +++ /dev/null @@ -1,68 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:32 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt -| Design : CPU9bits -| Device : xc7k160ti -------------------------------------------------------------------------------------- - -Control Set Information - -Table of Contents ------------------ -1. Summary -2. Histogram -3. Flip-Flop Distribution -4. Detailed Control Set Information - -1. Summary ----------- - -+----------------------------------------------------------+-------+ -| Status | Count | -+----------------------------------------------------------+-------+ -| Number of unique control sets | 3 | -| Unused register locations in slices containing registers | 19 | -+----------------------------------------------------------+-------+ - - -2. Histogram ------------- - -+--------+--------------+ -| Fanout | Control Sets | -+--------+--------------+ -| 3 | 1 | -| 9 | 2 | -+--------+--------------+ - - -3. Flip-Flop Distribution -------------------------- - -+--------------+-----------------------+------------------------+-----------------+--------------+ -| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | -+--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 3 | 1 | -| No | No | Yes | 0 | 0 | -| No | Yes | No | 0 | 0 | -| Yes | No | No | 0 | 0 | -| Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 18 | 8 | -+--------------+-----------------------+------------------------+-----------------+--------------+ - - -4. Detailed Control Set Information ------------------------------------ - -+----------------+----------------------------+------------------+------------------+----------------+ -| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | -+----------------+----------------------------+------------------+------------------+----------------+ -| clk_IBUF_BUFG | | | 1 | 3 | -| clk_IBUF_BUFG | FetchU/PC/E[0] | reset_IBUF | 4 | 9 | -| clk_IBUF_BUFG | FetchU/PC/Dout_reg[0]_1[0] | reset_IBUF | 4 | 9 | -+----------------+----------------------------+------------------+------------------+----------------+ - - diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb b/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb deleted file mode 100644 index 0158a2a..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_drc_opted.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt b/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt deleted file mode 100644 index df76f81..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt +++ /dev/null @@ -1,61 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:22 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx -| Design : CPU9bits -| Device : xc7k160tifbg484-2L -| Speed File : -2L -| Design State : Synthesized ---------------------------------------------------------------------------------------------------------------- - -Report DRC - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Ruledeck: default - Max violations: - Violations found: 3 -+----------+------------------+-----------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+----------+------------------+-----------------------------------------------------+------------+ -| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | -| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | -| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | -+----------+------------------+-----------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -NSTD-1#1 Critical Warning -Unspecified I/O Standard -12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset. -Related violations: - -UCIO-1#1 Critical Warning -Unconstrained Logical Port -12 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset. -Related violations: - -CFGBVS-1#1 Warning -Missing CFGBVS and CONFIG_VOLTAGE Design Properties -Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -Related violations: - - diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb b/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb deleted file mode 100644 index 0158a2a..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_drc_routed.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt deleted file mode 100644 index cf64052..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt +++ /dev/null @@ -1,61 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:17 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx -| Design : CPU9bits -| Device : xc7k160tifbg484-2L -| Speed File : -2L -| Design State : Fully Routed ------------------------------------------------------------------------------------------------------------------- - -Report DRC - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Ruledeck: default - Max violations: - Violations found: 3 -+----------+------------------+-----------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+----------+------------------+-----------------------------------------------------+------------+ -| NSTD-1 | Critical Warning | Unspecified I/O Standard | 1 | -| UCIO-1 | Critical Warning | Unconstrained Logical Port | 1 | -| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | -+----------+------------------+-----------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -NSTD-1#1 Critical Warning -Unspecified I/O Standard -12 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset. -Related violations: - -UCIO-1#1 Critical Warning -Unconstrained Logical Port -12 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: result[8:0], clk, done, reset. -Related violations: - -CFGBVS-1#1 Warning -Missing CFGBVS and CONFIG_VOLTAGE Design Properties -Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -Related violations: - - diff --git a/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt deleted file mode 100644 index a4df712..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt +++ /dev/null @@ -1,526 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:32 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_io -file CPU9bits_io_placed.rpt -| Design : CPU9bits -| Device : xc7k160ti -| Speed File : -2L -| Package : fbg484 -| Package Version : FINAL 2012-06-26 -| Package Pin Delay Version : VERS. 2.0 2012-06-26 -------------------------------------------------------------------------------------------------- - -IO Information - -Table of Contents ------------------ -1. Summary -2. IO Assignments by Package Pin - -1. Summary ----------- - -+---------------+ -| Total User IO | -+---------------+ -| 12 | -+---------------+ - - -2. IO Assignments by Package Pin --------------------------------- - -+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization | -+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| A3 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | | -| A4 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | | -| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A8 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| A9 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| A10 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| A11 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| A13 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | | -| A14 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | | -| A15 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | | -| A16 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | | -| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| A18 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | | -| A19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | | -| A20 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | | -| A21 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | | -| A22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AA1 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AA2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AA3 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AA4 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AA5 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA6 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| AA8 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA9 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA10 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA11 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AA13 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| AA14 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA15 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA16 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA17 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| AA18 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA19 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA20 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA21 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| AA22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AB1 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AB2 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AB3 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| AB4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| AB5 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB6 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AB10 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB11 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB12 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB13 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| AB14 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| AB15 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB16 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB17 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB18 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| AB20 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB21 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -| AB22 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| B1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | | -| B2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | | -| B3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B5 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | | -| B6 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | | -| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B8 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| B9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B10 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| B11 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| B12 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | | -| B13 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | | -| B14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| B15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | | -| B16 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | | -| B17 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | | -| B18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | | -| B19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| B20 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | | -| B21 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | | -| B22 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | | -| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| C3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | | -| C4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | | -| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C8 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| C9 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | -| C10 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| C11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | -| C12 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | | -| C13 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | | -| C14 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | | -| C15 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | | -| C16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| C17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | | -| C18 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | | -| C19 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | | -| C20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | -| C21 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| C22 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | -| D1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | | -| D2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | | -| D3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | | -| D6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | | -| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | -| D9 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| D10 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| D11 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| D12 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | | -| D13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| D14 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | | -| D15 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | | -| D16 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | | -| D17 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| D18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| D19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | | -| D20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | | -| D21 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | | -| D22 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | | -| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| E3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | | -| E4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | | -| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E8 | | High Range | IO_24_T3_16 | User IO | | 16 | | | | | | | | | | | | | | -| E9 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| E10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E11 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| E12 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| E13 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| E14 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | | -| E15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| E16 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| E17 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| E18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | | -| E19 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | | -| E20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| E21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | | -| E22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | | -| F1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | | -| F2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | | -| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | | -| F6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | | -| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F8 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | -| F9 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| F11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| F12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | -| F13 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| F14 | | High Range | IO_6_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | | -| F15 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | | -| F16 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | | -| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| F18 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | | -| F19 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | | -| F20 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | | -| F21 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | | -| F22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | | -| G3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | | -| G4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | | -| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | | -| G7 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | | -| G8 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | -| G9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | | -| G10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| G11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| G12 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| G13 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | | -| G14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| G15 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | | -| G16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | | -| G17 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | | -| G18 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | | -| G19 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| G20 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | | -| G21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | -| G22 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | | -| H1 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | | -| H2 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | | -| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H6 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | | -| H7 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | | -| H8 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | | -| H9 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | | -| H10 | | High Range | IO_18_T2_16 | User IO | | 16 | | | | | | | | | | | | | | -| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H12 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | | -| H13 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| H14 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | | -| H15 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | | -| H16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | | -| H17 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | | -| H18 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | | -| H19 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | | -| H20 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| H21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| H22 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | | -| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J4 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | | -| J5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | | -| J6 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | | -| J7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | -| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| J16 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | | -| J17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | | -| J18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| J19 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | | -| J20 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| J21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | | -| J22 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | | -| K1 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| K2 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| K3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| K4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | | -| K5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | | -| K7 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | | -| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| K11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | | -| K12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | | -| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| K15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| K16 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | | -| K17 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | -| K18 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| K19 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | | -| K20 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| K21 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| K22 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | | -| L1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L3 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| L4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| L5 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| L6 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | | -| L7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | | -| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | | -| L12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | | -| L13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| L16 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| L18 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | | -| L19 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| L20 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| L21 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | | -| L22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M1 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| M2 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| M3 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| M4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| M5 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| M6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | | -| M7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | | -| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| M11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | | -| M12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | | -| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M16 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | | -| M17 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| M18 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| M19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| M20 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | | -| M21 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | | -| M22 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| N1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| N2 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| N3 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | | -| N4 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| N5 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| N6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | | -| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | -| N12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | | -| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| N16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| N17 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | | -| N18 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| N19 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | | -| N20 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | | -| N21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| N22 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | | -| P1 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| P2 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P4 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| P5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| P6 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | -| P7 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | | -| P8 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| P11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| P16 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | | -| P17 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | | -| P18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | | -| P19 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | | -| P20 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | | -| P21 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | | -| P22 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | | -| R1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| R2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| R3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| R4 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| R5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| R6 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| R7 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R9 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | | -| R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | | -| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| R16 | reset | High Range | IO_L20P_T3_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | -| R17 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | | -| R18 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | | -| R19 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | | -| R20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| R21 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | | -| R22 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | | -| T1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| T2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| T3 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| T4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| T5 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| T6 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | | -| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| T8 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| T9 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| T10 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| T11 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| T12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| T13 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| T14 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | | -| T15 | result[2] | High Range | IO_L24P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| T16 | done | High Range | IO_L20N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| T18 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| T19 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | | -| T20 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| T21 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| T22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| U1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | | -| U2 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| U3 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| U4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| U5 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| U6 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| U7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| U8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| U9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| U10 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| U11 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| U12 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | | -| U13 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| U15 | result[1] | High Range | IO_L24N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| U16 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | | -| U17 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| U18 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | | -| U19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| U20 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | -| U21 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| U22 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| V1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V2 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| V3 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| V4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| V5 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | | -| V6 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| V7 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| V8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| V9 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| V10 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| V11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V12 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| V13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| V14 | result[0] | High Range | IO_25_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| V15 | result[4] | High Range | IO_L23P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| V16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| V17 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | | -| V18 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| V19 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| V20 | clk | High Range | IO_L11P_T1_SRCC_13 | INPUT | LVCMOS18* | 13 | | | | NONE | | UNFIXED | | | | NONE | | | | -| V21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| V22 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| W1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| W2 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | | -| W3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | | -| W4 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | | -| W5 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| W6 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| W7 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| W8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| W9 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| W10 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| W11 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | | -| W12 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | | -| W13 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| W14 | result[6] | High Range | IO_L22P_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| W15 | result[3] | High Range | IO_L23N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| W16 | result[8] | High Range | IO_L21P_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| W17 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| W18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| W19 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| W20 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| W21 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| W22 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y2 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y3 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y4 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | | -| Y5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| Y6 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y7 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y8 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y9 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | | -| Y11 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y12 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y13 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | | -| Y14 | result[5] | High Range | IO_L22N_T3_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| Y15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | -| Y16 | result[7] | High Range | IO_L21N_T3_DQS_13 | OUTPUT | LVCMOS18* | 13 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | -| Y17 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y18 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y19 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y20 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 1.80 | | | | | | | | | -| Y21 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -| Y22 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | | -+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+ -* Default value -** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements. - - diff --git a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb deleted file mode 100644 index 1cf5964..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt deleted file mode 100644 index 82180e8..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt +++ /dev/null @@ -1,145 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:19 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx -| Design : CPU9bits -| Device : xc7k160tifbg484-2L -| Speed File : -2L -| Design State : Fully Routed --------------------------------------------------------------------------------------------------------------------------------------------------------------- - -Report Methodology - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Max violations: - Violations found: 22 -+-----------+----------+-----------------------------+------------+ -| Rule | Severity | Description | Violations | -+-----------+----------+-----------------------------+------------+ -| TIMING-17 | Warning | Non-clocked sequential cell | 22 | -+-----------+----------+-----------------------------+------------+ - -2. REPORT DETAILS ------------------ -TIMING-17#1 Warning -Non-clocked sequential cell -The clock pin FetchU/PC/Dout_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#2 Warning -Non-clocked sequential cell -The clock pin FetchU/PC/Dout_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#3 Warning -Non-clocked sequential cell -The clock pin FetchU/PC/Dout_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#4 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#5 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#6 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#7 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#8 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#9 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#10 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#11 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[7]/C is not reached by a timing clock -Related violations: - -TIMING-17#12 Warning -Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[8]/C is not reached by a timing clock -Related violations: - -TIMING-17#13 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[0]/C is not reached by a timing clock -Related violations: - -TIMING-17#14 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[1]/C is not reached by a timing clock -Related violations: - -TIMING-17#15 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[2]/C is not reached by a timing clock -Related violations: - -TIMING-17#16 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[3]/C is not reached by a timing clock -Related violations: - -TIMING-17#17 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[4]/C is not reached by a timing clock -Related violations: - -TIMING-17#18 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[5]/C is not reached by a timing clock -Related violations: - -TIMING-17#19 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[6]/C is not reached by a timing clock -Related violations: - -TIMING-17#20 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[7]/C is not reached by a timing clock -Related violations: - -TIMING-17#21 Warning -Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[8]/C is not reached by a timing clock -Related violations: - -TIMING-17#22 Warning -Non-clocked sequential cell -The clock pin dM/memory_reg/CLKARDCLK is not reached by a timing clock -Related violations: - - diff --git a/lab2CA.runs/impl_1/CPU9bits_opt.dcp b/lab2CA.runs/impl_1/CPU9bits_opt.dcp deleted file mode 100644 index acc9d4f..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_opt.dcp and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_placed.dcp b/lab2CA.runs/impl_1/CPU9bits_placed.dcp deleted file mode 100644 index 5677e49..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_placed.dcp and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_power_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_power_routed.rpt deleted file mode 100644 index 42a27a1..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_power_routed.rpt +++ /dev/null @@ -1,151 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:20 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx -| Design : CPU9bits -| Device : xc7k160tifbg484-2L -| Design State : routed -| Grade : industrial -| Process : typical -| Characterization : Production ----------------------------------------------------------------------------------------------------------------------------------------------- - -Power Report - -Table of Contents ------------------ -1. Summary -1.1 On-Chip Components -1.2 Power Supply Summary -1.3 Confidence Level -2. Settings -2.1 Environment -2.2 Clock Constraints -3. Detailed Reports -3.1 By Hierarchy - -1. Summary ----------- - -+--------------------------+--------------+ -| Total On-Chip Power (W) | 11.172 | -| Design Power Budget (W) | Unspecified* | -| Power Budget Margin (W) | NA | -| Dynamic (W) | 11.030 | -| Device Static (W) | 0.142 | -| Effective TJA (C/W) | 2.5 | -| Max Ambient (C) | 72.4 | -| Junction Temperature (C) | 52.6 | -| Confidence Level | Low | -| Setting File | --- | -| Simulation Activity File | --- | -| Design Nets Matched | NA | -+--------------------------+--------------+ -* Specify Design Power Budget using, set_operating_conditions -design_power_budget - - -1.1 On-Chip Components ----------------------- - -+----------------+-----------+----------+-----------+-----------------+ -| On-Chip | Power (W) | Used | Available | Utilization (%) | -+----------------+-----------+----------+-----------+-----------------+ -| Slice Logic | 1.248 | 107 | --- | --- | -| LUT as Logic | 1.231 | 73 | 101400 | 0.07 | -| Register | 0.012 | 21 | 202800 | 0.01 | -| BUFG | 0.005 | 1 | 32 | 3.13 | -| Others | 0.000 | 4 | --- | --- | -| Signals | 1.328 | 114 | --- | --- | -| Block RAM | 0.060 | 0.5 | 325 | 0.15 | -| I/O | 8.393 | 12 | 285 | 4.21 | -| Static Power | 0.142 | | | | -| Total | 11.172 | | | | -+----------------+-----------+----------+-----------+-----------------+ - - -1.2 Power Supply Summary ------------------------- - -+-----------+-------------+-----------+-------------+------------+ -| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | -+-----------+-------------+-----------+-------------+------------+ -| Vccint | 0.950 | 2.849 | 2.775 | 0.074 | -| Vccaux | 1.800 | 0.707 | 0.687 | 0.020 | -| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | -| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | -| Vcco18 | 1.800 | 3.975 | 3.974 | 0.001 | -| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | -| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | -| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | -| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccbram | 0.950 | 0.007 | 0.005 | 0.002 | -| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | -| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | -| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccadc | 1.800 | 0.018 | 0.000 | 0.018 | -+-----------+-------------+-----------+-------------+------------+ - - -1.3 Confidence Level --------------------- - -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ -| User Input Data | Confidence | Details | Action | -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ -| Design implementation state | High | Design is routed | | -| Clock nodes activity | Low | User specified less than 75% of clocks | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view | -| I/O nodes activity | Low | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view | -| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views | -| Device models | High | Device models are Production | | -| | | | | -| Overall confidence level | Low | | | -+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+ - - -2. Settings ------------ - -2.1 Environment ---------------- - -+-----------------------+--------------------------+ -| Ambient Temp (C) | 25.0 | -| ThetaJA (C/W) | 2.5 | -| Airflow (LFM) | 250 | -| Heat Sink | medium (Medium Profile) | -| ThetaSA (C/W) | 4.2 | -| Board Selection | medium (10"x10") | -| # of Board Layers | 12to15 (12 to 15 Layers) | -| Board Temperature (C) | 25.0 | -+-----------------------+--------------------------+ - - -2.2 Clock Constraints ---------------------- - -+-------+--------+-----------------+ -| Clock | Domain | Constraint (ns) | -+-------+--------+-----------------+ - - -3. Detailed Reports -------------------- - -3.1 By Hierarchy ----------------- - -+----------+-----------+ -| Name | Power (W) | -+----------+-----------+ -| CPU9bits | 11.030 | -| FetchU | 1.191 | -| PC | 1.191 | -| RF | 1.317 | -| r0 | 0.812 | -| r1 | 0.506 | -| dM | 0.113 | -+----------+-----------+ - - diff --git a/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb b/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb deleted file mode 100644 index f938afd..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_route_status.pb b/lab2CA.runs/impl_1/CPU9bits_route_status.pb deleted file mode 100644 index a8cf179..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_route_status.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_route_status.rpt b/lab2CA.runs/impl_1/CPU9bits_route_status.rpt deleted file mode 100644 index 368950c..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_route_status.rpt +++ /dev/null @@ -1,11 +0,0 @@ -Design Route Status - : # nets : - ------------------------------------------- : ----------- : - # of logical nets.......................... : 128 : - # of nets not needing routing.......... : 12 : - # of internally routed nets........ : 12 : - # of routable nets..................... : 116 : - # of fully routed nets............. : 116 : - # of nets with routing errors.......... : 0 : - ------------------------------------------- : ----------- : - diff --git a/lab2CA.runs/impl_1/CPU9bits_routed.dcp b/lab2CA.runs/impl_1/CPU9bits_routed.dcp deleted file mode 100644 index 736cead..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_routed.dcp and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_tb.vdi b/lab2CA.runs/impl_1/CPU9bits_tb.vdi deleted file mode 100644 index b2588e7..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_tb.vdi +++ /dev/null @@ -1,173 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 18:38:44 2019 -# Process ID: 13064 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 -# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source CPU9bits_tb.tcl -notrace -Command: link_design -top CPU9bits_tb -part xc7k160tifbg484-2L -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7k160tifbg484-2L -INFO: [Project 1-570] Preparing netlist for logic optimization -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 579.477 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 579.477 ; gain = 327.758 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 583.891 ; gain = 4.082 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: f67b9b0d - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1077.012 ; gain = 493.121 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: f67b9b0d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1167.297 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: f67b9b0d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1167.297 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: f67b9b0d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: f67b9b0d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1167.297 ; gain = 587.559 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx -Command: report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1192.641 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1192.641 ; gain = 0.328 -Phase 1 Placer Initialization | Checksum: 00000000 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1192.641 ; gain = 0.328 -ERROR: [Place 30-494] The design is empty -Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports. -Ending Placer Task | Checksum: 00000000 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1192.641 ; gain = 0.328 -INFO: [Common 17-83] Releasing license: Implementation -36 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered. -place_design failed -ERROR: [Common 17-69] Command failed: Placer could not place all instances -INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 18:39:16 2019... diff --git a/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb b/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb deleted file mode 100644 index 70698d1..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt b/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt deleted file mode 100644 index f3fdc2b..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt +++ /dev/null @@ -1,49 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sun Mar 24 18:39:15 2019 -| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) -| Command : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx -| Design : CPU9bits_tb -| Device : xc7k160tifbg484-2L -| Speed File : -2L -| Design State : Fully Routed ------------------------------------------------------------------------------------------------------------------------- - -Report DRC - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Ruledeck: default - Max violations: - Violations found: 1 -+----------+----------+-----------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+----------+----------+-----------------------------------------------------+------------+ -| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | -+----------+----------+-----------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -CFGBVS-1#1 Warning -Missing CFGBVS and CONFIG_VOLTAGE Design Properties -Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -Related violations: - - diff --git a/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp b/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp deleted file mode 100644 index a888ad7..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb b/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb deleted file mode 100644 index 4526e93..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.pb +++ /dev/null @@ -1,2 +0,0 @@ - -2012.4’)Timing analysis from Implemented netlist. \ No newline at end of file diff --git a/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt deleted file mode 100644 index 606f9c2..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt +++ /dev/null @@ -1,173 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:20 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation -| Design : CPU9bits -| Device : 7k160ti-fbg484 -| Speed File : -2L PRODUCTION 1.12 2017-02-17 ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ - -Timing Summary Report - ------------------------------------------------------------------------------------------------- -| Timer Settings -| -------------- ------------------------------------------------------------------------------------------------- - - Enable Multi Corner Analysis : Yes - Enable Pessimism Removal : Yes - Pessimism Removal Resolution : Nearest Common Node - Enable Input Delay Default Clock : No - Enable Preset / Clear Arcs : No - Disable Flight Delays : No - Ignore I/O Paths : No - Timing Early Launch at Borrowing Latches : false - - Corner Analyze Analyze - Name Max Paths Min Paths - ------ --------- --------- - Slow Yes Yes - Fast Yes Yes - - - -check_timing report - -Table of Contents ------------------ -1. checking no_clock -2. checking constant_clock -3. checking pulse_width_clock -4. checking unconstrained_internal_endpoints -5. checking no_input_delay -6. checking no_output_delay -7. checking multiple_clock -8. checking generated_clocks -9. checking loops -10. checking partial_input_delay -11. checking partial_output_delay -12. checking latch_loops - -1. checking no_clock --------------------- - There are 22 register/latch pins with no clock driven by root clock pin: clk (HIGH) - - -2. checking constant_clock --------------------------- - There are 0 register/latch pins with constant_clock. - - -3. checking pulse_width_clock ------------------------------ - There are 0 register/latch pins which need pulse_width check - - -4. checking unconstrained_internal_endpoints --------------------------------------------- - There are 75 pins that are not constrained for maximum delay. (HIGH) - - There are 0 pins that are not constrained for maximum delay due to constant clock. - - -5. checking no_input_delay --------------------------- - There is 1 input port with no input delay specified. (HIGH) - - There are 0 input ports with no input delay but user has a false path constraint. - - -6. checking no_output_delay ---------------------------- - There are 10 ports with no output delay specified. (HIGH) - - There are 0 ports with no output delay but user has a false path constraint - - There are 0 ports with no output delay but with a timing clock defined on it or propagating through it - - -7. checking multiple_clock --------------------------- - There are 0 register/latch pins with multiple clocks. - - -8. checking generated_clocks ----------------------------- - There are 0 generated clocks that are not connected to a clock source. - - -9. checking loops ------------------ - There are 0 combinational loops in the design. - - -10. checking partial_input_delay --------------------------------- - There are 0 input ports with partial input delay specified. - - -11. checking partial_output_delay ---------------------------------- - There are 0 ports with partial output delay specified. - - -12. checking latch_loops ------------------------- - There are 0 combinational latch loops in the design through latch input - - - ------------------------------------------------------------------------------------------------- -| Design Timing Summary -| --------------------- ------------------------------------------------------------------------------------------------- - - WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints - ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - NA NA NA NA NA NA NA NA NA NA NA NA - - -There are no user specified timing constraints. - - ------------------------------------------------------------------------------------------------- -| Clock Summary -| ------------- ------------------------------------------------------------------------------------------------- - - ------------------------------------------------------------------------------------------------- -| Intra Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - - ------------------------------------------------------------------------------------------------- -| Inter Clock Table -| ----------------- ------------------------------------------------------------------------------------------------- - -From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- - - ------------------------------------------------------------------------------------------------- -| Other Path Groups Table -| ----------------------- ------------------------------------------------------------------------------------------------- - -Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ----------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- - - ------------------------------------------------------------------------------------------------- -| Timing Details -| -------------- ------------------------------------------------------------------------------------------------- - - diff --git a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb deleted file mode 100644 index 0e56dc6..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt deleted file mode 100644 index e85b036..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt +++ /dev/null @@ -1,211 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:32 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) -| Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb -| Design : CPU9bits -| Device : 7k160tifbg484-2L -| Design State : Fully Placed -------------------------------------------------------------------------------------------------------------- - -Utilization Design Information - -Table of Contents ------------------ -1. Slice Logic -1.1 Summary of Registers by Type -2. Slice Logic Distribution -3. Memory -4. DSP -5. IO and GT Specific -6. Clocking -7. Specific Feature -8. Primitives -9. Black Boxes -10. Instantiated Netlists - -1. Slice Logic --------------- - -+-------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------------+------+-------+-----------+-------+ -| Slice LUTs | 73 | 0 | 101400 | 0.07 | -| LUT as Logic | 73 | 0 | 101400 | 0.07 | -| LUT as Memory | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 21 | 0 | 202800 | 0.01 | -| Register as Flip Flop | 21 | 0 | 202800 | 0.01 | -| Register as Latch | 0 | 0 | 202800 | 0.00 | -| F7 Muxes | 0 | 0 | 50700 | 0.00 | -| F8 Muxes | 0 | 0 | 25350 | 0.00 | -+-------------------------+------+-------+-----------+-------+ - - -1.1 Summary of Registers by Type --------------------------------- - -+-------+--------------+-------------+--------------+ -| Total | Clock Enable | Synchronous | Asynchronous | -+-------+--------------+-------------+--------------+ -| 0 | _ | - | - | -| 0 | _ | - | Set | -| 0 | _ | - | Reset | -| 0 | _ | Set | - | -| 0 | _ | Reset | - | -| 0 | Yes | - | - | -| 0 | Yes | - | Set | -| 0 | Yes | - | Reset | -| 0 | Yes | Set | - | -| 21 | Yes | Reset | - | -+-------+--------------+-------------+--------------+ - - -2. Slice Logic Distribution ---------------------------- - -+--------------------------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+--------------------------------------------+------+-------+-----------+-------+ -| Slice | 21 | 0 | 25350 | 0.08 | -| SLICEL | 11 | 0 | | | -| SLICEM | 10 | 0 | | | -| LUT as Logic | 73 | 0 | 101400 | 0.07 | -| using O5 output only | 0 | | | | -| using O6 output only | 65 | | | | -| using O5 and O6 | 8 | | | | -| LUT as Memory | 0 | 0 | 35000 | 0.00 | -| LUT as Distributed RAM | 0 | 0 | | | -| LUT as Shift Register | 0 | 0 | | | -| Slice Registers | 21 | 0 | 202800 | 0.01 | -| Register driven from within the Slice | 4 | | | | -| Register driven from outside the Slice | 17 | | | | -| LUT in front of the register is unused | 0 | | | | -| LUT in front of the register is used | 17 | | | | -| Unique Control Sets | 3 | | 25350 | 0.01 | -+--------------------------------------------+------+-------+-----------+-------+ -* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. - - -3. Memory ---------- - -+-------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------------+------+-------+-----------+-------+ -| Block RAM Tile | 0.5 | 0 | 325 | 0.15 | -| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | -| RAMB18 | 1 | 0 | 650 | 0.15 | -| RAMB18E1 only | 1 | | | | -+-------------------+------+-------+-----------+-------+ -* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 - - -4. DSP ------- - -+-----------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------+------+-------+-----------+-------+ -| DSPs | 0 | 0 | 600 | 0.00 | -+-----------+------+-------+-----------+-------+ - - -5. IO and GT Specific ---------------------- - -+-----------------------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-----------------------------+------+-------+-----------+-------+ -| Bonded IOB | 12 | 0 | 285 | 4.21 | -| IOB Master Pads | 6 | | | | -| IOB Slave Pads | 5 | | | | -| Bonded IPADs | 0 | 0 | 14 | 0.00 | -| Bonded OPADs | 0 | 0 | 8 | 0.00 | -| PHY_CONTROL | 0 | 0 | 8 | 0.00 | -| PHASER_REF | 0 | 0 | 8 | 0.00 | -| OUT_FIFO | 0 | 0 | 32 | 0.00 | -| IN_FIFO | 0 | 0 | 32 | 0.00 | -| IDELAYCTRL | 0 | 0 | 8 | 0.00 | -| IBUFDS | 0 | 0 | 275 | 0.00 | -| GTXE2_COMMON | 0 | 0 | 1 | 0.00 | -| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 | -| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | -| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | -| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | -| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | -| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | -| ILOGIC | 0 | 0 | 285 | 0.00 | -| OLOGIC | 0 | 0 | 285 | 0.00 | -+-----------------------------+------+-------+-----------+-------+ - - -6. Clocking ------------ - -+------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+------------+------+-------+-----------+-------+ -| BUFGCTRL | 1 | 0 | 32 | 3.13 | -| BUFIO | 0 | 0 | 32 | 0.00 | -| MMCME2_ADV | 0 | 0 | 8 | 0.00 | -| PLLE2_ADV | 0 | 0 | 8 | 0.00 | -| BUFMRCE | 0 | 0 | 16 | 0.00 | -| BUFHCE | 0 | 0 | 120 | 0.00 | -| BUFR | 0 | 0 | 32 | 0.00 | -+------------+------+-------+-----------+-------+ - - -7. Specific Feature -------------------- - -+-------------+------+-------+-----------+-------+ -| Site Type | Used | Fixed | Available | Util% | -+-------------+------+-------+-----------+-------+ -| BSCANE2 | 0 | 0 | 4 | 0.00 | -| CAPTUREE2 | 0 | 0 | 1 | 0.00 | -| DNA_PORT | 0 | 0 | 1 | 0.00 | -| EFUSE_USR | 0 | 0 | 1 | 0.00 | -| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | -| ICAPE2 | 0 | 0 | 2 | 0.00 | -| PCIE_2_1 | 0 | 0 | 1 | 0.00 | -| STARTUPE2 | 0 | 0 | 1 | 0.00 | -| XADC | 0 | 0 | 1 | 0.00 | -+-------------+------+-------+-----------+-------+ - - -8. Primitives -------------- - -+----------+------+---------------------+ -| Ref Name | Used | Functional Category | -+----------+------+---------------------+ -| LUT6 | 37 | LUT | -| LUT4 | 27 | LUT | -| FDRE | 21 | Flop & Latch | -| OBUF | 10 | IO | -| LUT5 | 10 | LUT | -| LUT2 | 4 | LUT | -| LUT3 | 3 | LUT | -| IBUF | 2 | IO | -| RAMB18E1 | 1 | Block Memory | -| BUFG | 1 | Clock | -+----------+------+---------------------+ - - -9. Black Boxes --------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - -10. Instantiated Netlists -------------------------- - -+----------+------+ -| Ref Name | Used | -+----------+------+ - - diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml deleted file mode 100644 index fdb8b46..0000000 --- a/lab2CA.runs/impl_1/gen_run.xml +++ /dev/null @@ -1,167 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/lab2CA.runs/impl_1/htr.txt b/lab2CA.runs/impl_1/htr.txt deleted file mode 100644 index a32836e..0000000 --- a/lab2CA.runs/impl_1/htr.txt +++ /dev/null @@ -1,9 +0,0 @@ -REM -REM Vivado(TM) -REM htr.txt: a Vivado-generated description of how-to-repeat the -REM the basic steps of a run. Note that runme.bat/sh needs -REM to be invoked for Vivado to track run status. -REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -REM - -vivado -log CPU9bits.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace diff --git a/lab2CA.runs/impl_1/init_design.pb b/lab2CA.runs/impl_1/init_design.pb deleted file mode 100644 index 0a2f9c2..0000000 Binary files a/lab2CA.runs/impl_1/init_design.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/opt_design.pb b/lab2CA.runs/impl_1/opt_design.pb deleted file mode 100644 index 50748ca..0000000 Binary files a/lab2CA.runs/impl_1/opt_design.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/place_design.pb b/lab2CA.runs/impl_1/place_design.pb deleted file mode 100644 index a40d85d..0000000 Binary files a/lab2CA.runs/impl_1/place_design.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/route_design.pb b/lab2CA.runs/impl_1/route_design.pb deleted file mode 100644 index 7d7b234..0000000 Binary files a/lab2CA.runs/impl_1/route_design.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/vivado.jou b/lab2CA.runs/impl_1/vivado.jou deleted file mode 100644 index 5c4b72f..0000000 --- a/lab2CA.runs/impl_1/vivado.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 30 15:53:31 2019 -# Process ID: 13696 -# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1 -# Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace -# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi -# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source CPU9bits.tcl -notrace diff --git a/lab2CA.runs/impl_1/vivado.pb b/lab2CA.runs/impl_1/vivado.pb deleted file mode 100644 index cb078e2..0000000 Binary files a/lab2CA.runs/impl_1/vivado.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/vivado_13064.backup.jou b/lab2CA.runs/impl_1/vivado_13064.backup.jou deleted file mode 100644 index 9cf4c69..0000000 --- a/lab2CA.runs/impl_1/vivado_13064.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 18:38:44 2019 -# Process ID: 13064 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 -# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source CPU9bits_tb.tcl -notrace diff --git a/lab2CA.runs/synth_1/CPU9bits.dcp b/lab2CA.runs/synth_1/CPU9bits.dcp index 8093ba8..33a3c45 100644 Binary files a/lab2CA.runs/synth_1/CPU9bits.dcp and b/lab2CA.runs/synth_1/CPU9bits.dcp differ diff --git a/lab2CA.runs/synth_1/CPU9bits.tcl b/lab2CA.runs/synth_1/CPU9bits.tcl index 623234b..ddbc3d6 100644 --- a/lab2CA.runs/synth_1/CPU9bits.tcl +++ b/lab2CA.runs/synth_1/CPU9bits.tcl @@ -17,8 +17,6 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 create_project -in_memory -part xc7k160tifbg484-2L set_param project.singleFileAddWarning.threshold 0 diff --git a/lab2CA.runs/synth_1/CPU9bits.vds b/lab2CA.runs/synth_1/CPU9bits.vds index a64412c..19e8641 100644 --- a/lab2CA.runs/synth_1/CPU9bits.vds +++ b/lab2CA.runs/synth_1/CPU9bits.vds @@ -2,8 +2,8 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 30 15:52:45 2019 -# Process ID: 9028 +# Start of session at: Sat Apr 6 14:00:40 2019 +# Process ID: 8416 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds @@ -15,9 +15,9 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 18388 +INFO: Helper process launched with PID 19172 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 364.258 ; gain = 100.730 +Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 362.617 ; gain = 101.777 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'CPU9bits' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] INFO: [Synth 8-6157] synthesizing module 'instructionMemory' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/instructionMemory.v:3] @@ -26,76 +26,77 @@ INFO: [Synth 8-6157] synthesizing module 'dataMemory' [C:/REPOSITORIES/Education INFO: [Synth 8-6155] done synthesizing module 'dataMemory' (2#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/dataMemory.v:3] INFO: [Synth 8-6157] synthesizing module 'RegFile' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] INFO: [Synth 8-6157] synthesizing module 'decoder' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:266] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:268] INFO: [Synth 8-6155] done synthesizing module 'decoder' (3#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:261] -INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766] -INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:766] -INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:401] -INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:396] +INFO: [Synth 8-6157] synthesizing module 'register' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] +INFO: [Synth 8-6155] done synthesizing module 'register' (4#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:777] +INFO: [Synth 8-6157] synthesizing module 'mux_4_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:412] +INFO: [Synth 8-6155] done synthesizing module 'mux_4_1' (5#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:407] INFO: [Synth 8-6155] done synthesizing module 'RegFile' (6#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/RegFile.v:3] INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (7#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (8#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:56] -INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:331] -INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:325] +INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:342] +INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (9#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:336] INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (10#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] -INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1300] -INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1365] -INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676] -INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:676] -INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1365] -INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1300] -INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713] -INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:713] -INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632] -INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:632] +INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] +INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] +INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] +INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (11#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:687] +INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (12#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1376] +INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (13#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1311] +INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] +INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (14#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:724] +INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] +INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (15#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:643] INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (16#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:175] -INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:842] -INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:842] -INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:916] -INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:916] -INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:879] -INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:879] -INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309] -INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:309] -INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1414] -INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1414] -INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:530] -INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:524] +INFO: [Synth 8-6157] synthesizing module 'shift_left' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] +INFO: [Synth 8-6155] done synthesizing module 'shift_left' (17#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:853] +INFO: [Synth 8-6157] synthesizing module 'shift_right_logical' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_logical' (18#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:927] +INFO: [Synth 8-6157] synthesizing module 'shift_right_arithmetic' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6155] done synthesizing module 'shift_right_arithmetic' (19#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:890] +INFO: [Synth 8-6157] synthesizing module 'less_than' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] +INFO: [Synth 8-6155] done synthesizing module 'less_than' (20#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:320] +INFO: [Synth 8-6157] synthesizing module 'BEQ' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] +INFO: [Synth 8-6155] done synthesizing module 'BEQ' (21#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:1425] +INFO: [Synth 8-6157] synthesizing module 'mux_16_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:541] +INFO: [Synth 8-6155] done synthesizing module 'mux_16_1' (22#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:535] INFO: [Synth 8-6155] done synthesizing module 'ALU' (23#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ALU.v:3] INFO: [Synth 8-6157] synthesizing module 'ControlUnit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:13] INFO: [Synth 8-6155] done synthesizing module 'ControlUnit' (24#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/ControlUnit.v:3] -INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:985] -INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:985] -INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339] -INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:345] -INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:339] +INFO: [Synth 8-6157] synthesizing module 'sign_extend_3bit' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] +INFO: [Synth 8-6155] done synthesizing module 'sign_extend_3bit' (25#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:996] +INFO: [Synth 8-6157] synthesizing module 'bit1_mux_2_1' [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] +INFO: [Synth 8-226] default block is never used [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:356] +INFO: [Synth 8-6155] done synthesizing module 'bit1_mux_2_1' (26#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:350] INFO: [Synth 8-6155] done synthesizing module 'CPU9bits' (27#1) [C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.srcs/sources_1/new/CPU9bits.v:3] +WARNING: [Synth 8-3331] design dataMemory has unconnected port address[8] +WARNING: [Synth 8-3331] design dataMemory has unconnected port address[7] --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355 +Finished Synthesize : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355 +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k160tifbg484-2L --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 420.883 ; gain = 157.355 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 418.656 ; gain = 157.816 +--------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7k160tifbg484-2L --------------------------------------------------------------------------------- -INFO: [Synth 8-5544] ROM "memory" won't be mapped to Block RAM because address size (3) smaller than threshold (5) ---------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 420.883 ; gain = 157.355 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 418.656 ; gain = 157.816 --------------------------------------------------------------------------------- INFO: [Synth 8-223] decloning instance 'SE1' (sign_extend_3bit) to 'SE3' @@ -114,11 +115,11 @@ Detailed RTL Component Info : +---Registers : 9 Bit Registers := 10 +---RAMs : - 4K Bit RAMs := 1 + 909 Bit RAMs := 1 +---Muxes : - 7 Input 9 Bit Muxes := 1 4 Input 9 Bit Muxes := 5 2 Input 9 Bit Muxes := 8 + 2 Input 4 Bit Muxes := 2 4 Input 4 Bit Muxes := 2 16 Input 4 Bit Muxes := 1 2 Input 3 Bit Muxes := 2 @@ -139,19 +140,16 @@ Detailed RTL Component Info : +---Muxes : 4 Input 9 Bit Muxes := 1 8 Input 2 Bit Muxes := 1 -Module instructionMemory -Detailed RTL Component Info : -+---Muxes : - 7 Input 9 Bit Muxes := 1 Module dataMemory Detailed RTL Component Info : +---Registers : 9 Bit Registers := 1 +---RAMs : - 4K Bit RAMs := 1 + 909 Bit RAMs := 1 Module decoder Detailed RTL Component Info : +---Muxes : + 2 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 Module register Detailed RTL Component Info : @@ -199,24 +197,33 @@ Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- Warning: Parallel synthesis criteria is not met --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- +ROM: ++------------------+------------+---------------+----------------+ +|Module Name | RTL Object | Depth x Width | Implemented As | ++------------------+------------+---------------+----------------+ +|instructionMemory | p_0_out | 64x9 | LUT | +|CPU9bits | p_0_out | 64x9 | LUT | ++------------------+------------+---------------+----------------+ + + Block RAM: Preliminary Mapping Report (see note below) +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ -|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 | +|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 | +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- -INFO: [Synth 8-6837] The timing for the instance i_1/dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. +INFO: [Synth 8-6837] The timing for the instance i_0/dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. Report RTL Partitions: +-+--------------+------------+----------+ @@ -228,7 +235,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting @@ -238,7 +245,7 @@ Block RAM: Final Mapping Report +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ |Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ -|dataMemory: | memory_reg | 512 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 | +|dataMemory: | memory_reg | 128 x 9(NO_CHANGE) | W | R | | | | Port A | 1 | 0 | +------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+ --------------------------------------------------------------------------------- @@ -255,7 +262,7 @@ Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-6837] The timing for the instance dM/memory_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -279,7 +286,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- Report Check Netlist: @@ -292,7 +299,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -304,25 +311,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -339,51 +346,59 @@ Report Cell Usage: | |Cell |Count | +------+---------+------+ |1 |BUFG | 1| -|2 |LUT2 | 4| -|3 |LUT3 | 3| -|4 |LUT4 | 27| -|5 |LUT5 | 10| -|6 |LUT6 | 37| -|7 |RAMB18E1 | 1| -|8 |FDRE | 21| -|9 |IBUF | 2| -|10 |OBUF | 10| +|2 |LUT2 | 13| +|3 |LUT3 | 21| +|4 |LUT4 | 23| +|5 |LUT5 | 33| +|6 |LUT6 | 135| +|7 |MUXF7 | 11| +|8 |RAMB18E1 | 1| +|9 |FDRE | 81| +|10 |IBUF | 2| +|11 |OBUF | 10| +------+---------+------+ Report Instance Areas: +------+---------+-----------+------+ | |Instance |Module |Cells | +------+---------+-----------+------+ -|1 |top | | 116| -|2 | FetchU |FetchUnit | 31| -|3 | PC |register_1 | 31| -|4 | RF |RegFile | 71| -|5 | r0 |register | 42| -|6 | r1 |register_0 | 29| -|7 | dM |dataMemory | 1| +|1 |top | | 331| +|2 | Bank |RegFile | 45| +|3 | r0 |register_5 | 15| +|4 | r1 |register_6 | 9| +|5 | r2 |register_7 | 11| +|6 | r3 |register_8 | 10| +|7 | FetchU |FetchUnit | 135| +|8 | PC |register_4 | 135| +|9 | RF |RegFile_0 | 137| +|10 | r0 |register | 87| +|11 | r1 |register_1 | 17| +|12 | r2 |register_2 | 14| +|13 | r3 |register_3 | 19| +|14 | dM |dataMemory | 1| +------+---------+-----------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 0 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 -Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 598.238 ; gain = 334.711 +Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 +Synthesis Optimization Complete : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 622.602 ; gain = 361.762 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 12 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 684.082 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 683.707 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -73 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +72 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 684.082 ; gain = 433.695 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 684.082 ; gain = 0.000 +synth_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 683.707 ; gain = 435.820 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 683.707 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sat Mar 30 15:53:22 2019... +INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 14:01:18 2019... diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb index 0e56dc6..14cb012 100644 Binary files a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb and b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.pb differ diff --git a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt index 2b9cc8b..336ac7e 100644 --- a/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt +++ b/lab2CA.runs/synth_1/CPU9bits_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:53:22 2019 +| Date : Sat Apr 6 14:01:18 2019 | Host : WM-G75VW running 64-bit major release (build 9200) | Command : report_utilization -file CPU9bits_utilization_synth.rpt -pb CPU9bits_utilization_synth.pb | Design : CPU9bits @@ -30,13 +30,13 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 73 | 0 | 101400 | 0.07 | -| LUT as Logic | 73 | 0 | 101400 | 0.07 | +| Slice LUTs* | 193 | 0 | 101400 | 0.19 | +| LUT as Logic | 193 | 0 | 101400 | 0.19 | | LUT as Memory | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 21 | 0 | 202800 | 0.01 | -| Register as Flip Flop | 21 | 0 | 202800 | 0.01 | +| Slice Registers | 81 | 0 | 202800 | 0.04 | +| Register as Flip Flop | 81 | 0 | 202800 | 0.04 | | Register as Latch | 0 | 0 | 202800 | 0.00 | -| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F7 Muxes | 11 | 0 | 50700 | 0.02 | | F8 Muxes | 0 | 0 | 25350 | 0.00 | +-------------------------+------+-------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. @@ -57,7 +57,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 21 | Yes | Reset | - | +| 81 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -152,13 +152,14 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| LUT6 | 37 | LUT | -| LUT4 | 27 | LUT | -| FDRE | 21 | Flop & Latch | +| LUT6 | 135 | LUT | +| FDRE | 81 | Flop & Latch | +| LUT5 | 33 | LUT | +| LUT4 | 23 | LUT | +| LUT3 | 21 | LUT | +| LUT2 | 13 | LUT | +| MUXF7 | 11 | MuxFx | | OBUF | 10 | IO | -| LUT5 | 10 | LUT | -| LUT2 | 4 | LUT | -| LUT3 | 3 | LUT | | IBUF | 2 | IO | | RAMB18E1 | 1 | Block Memory | | BUFG | 1 | Clock | diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index 6b9dffe..6b83595 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/lab2CA.runs/synth_1/vivado.jou b/lab2CA.runs/synth_1/vivado.jou index 1cb2f8d..fe3cd53 100644 --- a/lab2CA.runs/synth_1/vivado.jou +++ b/lab2CA.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 30 15:52:45 2019 -# Process ID: 9028 +# Start of session at: Sat Apr 6 14:00:40 2019 +# Process ID: 8416 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1 # Command line: vivado.exe -log CPU9bits.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU9bits.tcl # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.vds diff --git a/lab2CA.runs/synth_1/vivado.pb b/lab2CA.runs/synth_1/vivado.pb index 81e985f..6d9392f 100644 Binary files a/lab2CA.runs/synth_1/vivado.pb and b/lab2CA.runs/synth_1/vivado.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/CPU9bits.tcl b/lab2CA.sim/sim_1/behav/xsim/CPU9bits.tcl new file mode 100644 index 0000000..8243a08 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/CPU9bits.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 100000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/CPU9bits_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/CPU9bits_vlog.prj new file mode 100644 index 0000000..34fbace --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/CPU9bits_vlog.prj @@ -0,0 +1,16 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/ALU.v" \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ +"../../../../lab2CA.srcs/sources_1/new/ControlUnit.v" \ +"../../../../lab2CA.srcs/sources_1/new/FetchUnit.v" \ +"../../../../lab2CA.srcs/sources_1/new/RegFile.v" \ +"../../../../lab2CA.srcs/sources_1/new/dataMemory.v" \ +"../../../../lab2CA.srcs/sources_1/new/instructionMemory.v" \ +"../../../../lab2CA.srcs/sources_1/new/CPU9bits.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou index b4e6d63..d1b0d25 100644 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -2,10 +2,10 @@ # Webtalk v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Fri Mar 29 15:28:37 2019 -# Process ID: 28052 +# Start of session at: Sat Apr 6 13:17:03 2019 +# Process ID: 10700 # Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace # Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log # Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou #----------------------------------------------------------- diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou deleted file mode 100644 index 1dd23b5..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_11344.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 17:25:06 2019 -# Process ID: 11344 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/instructionMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou new file mode 100644 index 0000000..71a23ce --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_11564.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Apr 6 13:16:30 2019 +# Process ID: 11564 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou deleted file mode 100644 index 1b4851e..0000000 --- a/lab2CA.sim/sim_1/behav/xsim/webtalk_12056.backup.jou +++ /dev/null @@ -1,12 +0,0 @@ -#----------------------------------------------------------- -# Webtalk v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 17:34:31 2019 -# Process ID: 12056 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim -# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou -#----------------------------------------------------------- -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_28052.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_28052.backup.jou new file mode 100644 index 0000000..b4e6d63 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_28052.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Fri Mar 29 15:28:37 2019 +# Process ID: 28052 +# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/dataMemory_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/REPOSITORIES/Educational/Western -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb index a4feb66..029ca56 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xelab.pb and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/Compile_Options.txt new file mode 100644 index 0000000..e653d16 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "CPU9bits_behav" "xil_defaultlib.CPU9bits" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/obj/xsim_1.c new file mode 100644 index 0000000..90eeca3 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/obj/xsim_1.c @@ -0,0 +1,169 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_173(char*, char *); +extern void execute_388(char*, char *); +extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_390(char*, char *); +extern void execute_391(char*, char *); +extern void execute_393(char*, char *); +extern void execute_394(char*, char *); +extern void execute_395(char*, char *); +extern void execute_396(char*, char *); +extern void execute_397(char*, char *); +extern void execute_398(char*, char *); +extern void execute_399(char*, char *); +extern void execute_400(char*, char *); +extern void execute_401(char*, char *); +extern void execute_402(char*, char *); +extern void execute_403(char*, char *); +extern void execute_404(char*, char *); +extern void execute_405(char*, char *); +extern void execute_406(char*, char *); +extern void execute_407(char*, char *); +extern void execute_408(char*, char *); +extern void execute_409(char*, char *); +extern void execute_410(char*, char *); +extern void execute_411(char*, char *); +extern void execute_412(char*, char *); +extern void execute_3(char*, char *); +extern void execute_4(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_178(char*, char *); +extern void execute_179(char*, char *); +extern void execute_180(char*, char *); +extern void execute_181(char*, char *); +extern void execute_182(char*, char *); +extern void execute_183(char*, char *); +extern void execute_184(char*, char *); +extern void execute_10(char*, char *); +extern void execute_12(char*, char *); +extern void execute_20(char*, char *); +extern void execute_211(char*, char *); +extern void execute_213(char*, char *); +extern void execute_214(char*, char *); +extern void execute_192(char*, char *); +extern void execute_193(char*, char *); +extern void execute_52(char*, char *); +extern void execute_323(char*, char *); +extern void execute_324(char*, char *); +extern void execute_325(char*, char *); +extern void execute_326(char*, char *); +extern void execute_327(char*, char *); +extern void execute_328(char*, char *); +extern void execute_252(char*, char *); +extern void execute_233(char*, char *); +extern void execute_273(char*, char *); +extern void execute_274(char*, char *); +extern void execute_275(char*, char *); +extern void execute_276(char*, char *); +extern void execute_277(char*, char *); +extern void execute_278(char*, char *); +extern void execute_320(char*, char *); +extern void execute_321(char*, char *); +extern void execute_120(char*, char *); +extern void execute_122(char*, char *); +extern void execute_368(char*, char *); +extern void execute_153(char*, char *); +extern void execute_175(char*, char *); +extern void execute_176(char*, char *); +extern void execute_177(char*, char *); +extern void execute_413(char*, char *); +extern void execute_414(char*, char *); +extern void execute_415(char*, char *); +extern void execute_416(char*, char *); +extern void execute_417(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +extern void transaction_59(char*, char*, unsigned, unsigned, unsigned); +funcp funcTab[75] = {(funcp)execute_173, (funcp)execute_388, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_390, (funcp)execute_391, (funcp)execute_393, (funcp)execute_394, (funcp)execute_395, (funcp)execute_396, (funcp)execute_397, (funcp)execute_398, (funcp)execute_399, (funcp)execute_400, (funcp)execute_401, (funcp)execute_402, (funcp)execute_403, (funcp)execute_404, (funcp)execute_405, (funcp)execute_406, (funcp)execute_407, (funcp)execute_408, (funcp)execute_409, (funcp)execute_410, (funcp)execute_411, (funcp)execute_412, (funcp)execute_3, (funcp)execute_4, (funcp)execute_6, (funcp)execute_7, (funcp)execute_178, (funcp)execute_179, (funcp)execute_180, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)execute_184, (funcp)execute_10, (funcp)execute_12, (funcp)execute_20, (funcp)execute_211, (funcp)execute_213, (funcp)execute_214, (funcp)execute_192, (funcp)execute_193, (funcp)execute_52, (funcp)execute_323, (funcp)execute_324, (funcp)execute_325, (funcp)execute_326, (funcp)execute_327, (funcp)execute_328, (funcp)execute_252, (funcp)execute_233, (funcp)execute_273, (funcp)execute_274, (funcp)execute_275, (funcp)execute_276, (funcp)execute_277, (funcp)execute_278, (funcp)execute_320, (funcp)execute_321, (funcp)execute_120, (funcp)execute_122, (funcp)execute_368, (funcp)execute_153, (funcp)execute_175, (funcp)execute_176, (funcp)execute_177, (funcp)execute_413, (funcp)execute_414, (funcp)execute_415, (funcp)execute_416, (funcp)execute_417, (funcp)vlog_transfunc_eventcallback, (funcp)transaction_59}; +const int NumRelocateId= 75; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/CPU9bits_behav/xsim.reloc", (void **)funcTab, 75); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/CPU9bits_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/CPU9bits_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/CPU9bits_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/CPU9bits_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/CPU9bits_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..7c2a370 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Apr 6 14:02:33 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "f67bb5263bf851bf9c1beaa84fe1017c" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "21" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i7-3630QM CPU @ 2.40GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "2395 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "17.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "100 us" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.11_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "5928_KB" -context "xsim\\usage" +webtalk_transmit -clientid 4022637463 -regid "" -xml C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/xsim.mem new file mode 100644 index 0000000..09eb4f0 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb index b155e40..3fe1568 100644 Binary files a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb and b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb differ