diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index 8a7e8ba..f521d8d 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -499,73 +499,11 @@ module nor_9bit_tb();
     end
 endmodule
 
-
-module not_1bit(
-    input wire A,
-    output wire B);
-    
-    assign B = ~A;
-
-endmodule
-
-//testbench
-module not_1bit_tb();
-    reg a;
-    wire b;
-
-    not_1bit not0(
-        .A(a),
-        .B(b));
-        
-    initial begin
-        a = 0;
-        #5
-        a = 1;
-        #5
-        $finish;
-
-    end
-endmodule
-
 module not_9bit(
     input wire [8:0] A,
     output wire [8:0] B);
 
-    not_1bit not0(
-        .A(A[0]),
-        .B(B[0]));
-
-    not_1bit not1(
-        .A(A[1]),
-        .B(B[1]));
-        
-    not_1bit not2(
-        .A(A[2]),
-        .B(B[2]));
-        
-    not_1bit not3(
-        .A(A[3]),
-        .B(B[3]));
-        
-    not_1bit not4(
-        .A(A[4]),
-        .B(B[4]));
-        
-    not_1bit not5(
-        .A(A[5]),
-        .B(B[5]));
-        
-    not_1bit not6(
-        .A(A[6]),
-        .B(B[6]));
-        
-    not_1bit not7(
-        .A(A[7]),
-        .B(B[7]));
-        
-    not_1bit not8(
-        .A(A[8]),
-        .B(B[8]));
+    assign B = ~A;
 
 endmodule