diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index 652ae82..fd95878 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -17,40 +17,41 @@ This means code written to parse this file will need to be revisited each subseq - - + + + - - + + - + - + - - - - + + + + - + - + @@ -58,27 +59,28 @@ This means code written to parse this file will need to be revisited each subseq - - - + + + - + + - + - - - + + + - + @@ -86,14 +88,14 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + @@ -107,8 +109,9 @@ This means code written to parse this file will need to be revisited each subseq - + + @@ -117,21 +120,22 @@ This means code written to parse this file will need to be revisited each subseq - - + + + - - + + - + - + @@ -139,30 +143,30 @@ This means code written to parse this file will need to be revisited each subseq - + - + - - + + - + - + - + - + - + @@ -172,29 +176,31 @@ This means code written to parse this file will need to be revisited each subseq - + - + + + - + - + - + - +
diff --git a/lab2CA.runs/.jobs/vrs_config_58.xml b/lab2CA.runs/.jobs/vrs_config_58.xml new file mode 100644 index 0000000..b013dc9 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_58.xml @@ -0,0 +1,11 @@ + + + + + + + + + + + diff --git a/lab2CA.runs/impl_1/CPU9bits.tcl b/lab2CA.runs/impl_1/CPU9bits.tcl index 8e1b126..00d37da 100644 --- a/lab2CA.runs/impl_1/CPU9bits.tcl +++ b/lab2CA.runs/impl_1/CPU9bits.tcl @@ -67,14 +67,15 @@ start_step init_design set ACTIVE_STEP init_design set rc [catch { create_msg_db init_design.pb + set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-10176-DESKTOP-8QFGS52/incrSyn create_project -in_memory -part xc7k160tifbg484-2L set_property design_mode GateLvl [current_fileset] set_param project.singleFileAddWarning.threshold 0 - set_property webtalk.parent_dir {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/wt} [current_project] - set_property parent.project_path {C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.xpr} [current_project] - set_property ip_output_repo {{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.cache/ip}} [current_project] + set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project] + set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project] + set_property ip_output_repo C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] - add_files -quiet {{C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp}} + add_files -quiet C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/CPU9bits.dcp link_design -top CPU9bits -part xc7k160tifbg484-2L close_msg_db -file init_design.pb } RESULT] diff --git a/lab2CA.runs/impl_1/CPU9bits.vdi b/lab2CA.runs/impl_1/CPU9bits.vdi index 492611e..df49391 100644 --- a/lab2CA.runs/impl_1/CPU9bits.vdi +++ b/lab2CA.runs/impl_1/CPU9bits.vdi @@ -2,29 +2,29 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Mar 30 15:53:31 2019 -# Process ID: 13696 -# Current directory: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1 +# Start of session at: Sat Apr 6 17:33:53 2019 +# Process ID: 9496 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 # Command line: vivado.exe -log CPU9bits.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits.tcl -notrace -# Log file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi -# Journal file: C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits.vdi +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou #----------------------------------------------------------- source CPU9bits.tcl -notrace Command: link_design -top CPU9bits -part xc7k160tifbg484-2L Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 -INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2018.3 INFO: [Device 21-403] Loading part xc7k160tifbg484-2L INFO: [Project 1-570] Preparing netlist for logic optimization -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 581.816 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 577.664 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 587.391 ; gain = 332.746 +link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 583.055 ; gain = 324.613 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' @@ -35,53 +35,53 @@ INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 603.059 ; gain = 15.668 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.719 . Memory (MB): peak = 595.676 ; gain = 12.621 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 257e1e38 +Ending Cache Timing Information Task | Checksum: 178a9fcd1 -Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1127.293 ; gain = 524.234 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1128.926 ; gain = 533.250 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 257e1e38 +Phase 1 Retarget | Checksum: 11e80142d -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1225.961 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1224.855 ; gain = 0.000 +INFO: [Opt 31-389] Phase Retarget created 1 cells and removed 1 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: 257e1e38 +Phase 2 Constant propagation | Checksum: 11e80142d -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.078 . Memory (MB): peak = 1225.961 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1224.855 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: 257e1e38 +Phase 3 Sweep | Checksum: 11e80142d -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.083 . Memory (MB): peak = 1225.961 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.098 . Memory (MB): peak = 1224.855 ; gain = 0.000 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: 257e1e38 +Phase 4 BUFG optimization | Checksum: 11e80142d -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.093 . Memory (MB): peak = 1225.961 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.103 . Memory (MB): peak = 1224.855 ; gain = 0.000 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 257e1e38 +Phase 5 Shift Register Optimization | Checksum: 8b9eda27 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.196 . Memory (MB): peak = 1225.961 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.145 . Memory (MB): peak = 1224.855 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: 257e1e38 +Phase 6 Post Processing Netlist | Checksum: 8b9eda27 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.199 . Memory (MB): peak = 1225.961 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.147 . Memory (MB): peak = 1224.855 ; gain = 0.000 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Opt_design Change Summary ========================= @@ -90,7 +90,7 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 0 | +| Retarget | 1 | 1 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | @@ -102,10 +102,10 @@ Opt_design Change Summary Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1225.961 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: 257e1e38 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1224.855 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 8b9eda27 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.206 . Memory (MB): peak = 1225.961 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.150 . Memory (MB): peak = 1224.855 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. @@ -124,40 +124,39 @@ Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 1 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 2 -Ending PowerOpt Patch Enables Task | Checksum: 257e1e38 +Ending PowerOpt Patch Enables Task | Checksum: 8b9eda27 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Ending Power Optimization Task | Checksum: 257e1e38 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1334.406 ; gain = 0.000 +Ending Power Optimization Task | Checksum: 8b9eda27 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1335.719 ; gain = 109.758 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.786 . Memory (MB): peak = 1334.406 ; gain = 109.551 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: 257e1e38 +Ending Final Cleanup Task | Checksum: 8b9eda27 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: 257e1e38 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 8b9eda27 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 28 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 1335.719 ; gain = 748.328 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 +opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1334.406 ; gain = 751.352 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated. +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx Command: report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt. +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt. report_drc completed successfully -report_drc: Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' @@ -175,128 +174,127 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1e0025bd +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 44f3ef01 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.014 . Memory (MB): peak = 1334.406 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: be8e8081 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b481c8c5 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 154227d99 +Phase 1.3 Build Placer Netlist Model | Checksum: 16bafe571 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 154227d99 +Phase 1.4 Constrain Clocks/Macros | Checksum: 16bafe571 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 1 Placer Initialization | Checksum: 154227d99 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 16bafe571 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 2 Global Placement Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 154227d99 +Phase 2.1 Floorplanning | Checksum: 16bafe571 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1334.406 ; gain = 0.000 WARNING: [Place 46-29] place_design is not in timing mode. Skip physical synthesis in placer -Phase 2 Global Placement | Checksum: 168f30526 +Phase 2 Global Placement | Checksum: 187ab5e99 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 168f30526 +Phase 3.1 Commit Multi Column Macros | Checksum: 187ab5e99 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10b26ca05 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 168760e64 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 171e1f517 +Phase 3.3 Area Swap Optimization | Checksum: 105becb87 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 171e1f517 +Phase 3.4 Pipeline Register Optimization | Checksum: 105becb87 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: eb242549 +Phase 3.5 Small Shape Detail Placement | Checksum: cd32f4e6 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: eb242549 +Phase 3.6 Re-assign LUT pins | Checksum: cd32f4e6 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: eb242549 +Phase 3.7 Pipeline Register Optimization | Checksum: cd32f4e6 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 3 Detail Placement | Checksum: eb242549 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 +Phase 3 Detail Placement | Checksum: cd32f4e6 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: eb242549 +Phase 4.1 Post Commit Optimization | Checksum: cd32f4e6 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: eb242549 +Phase 4.2 Post Placement Cleanup | Checksum: cd32f4e6 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: eb242549 +Phase 4.3 Placer Reporting | Checksum: cd32f4e6 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 4.4 Final Placement Cleanup | Checksum: eb242549 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000 +Phase 4.4 Final Placement Cleanup | Checksum: 18c80bbbe -Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: eb242549 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18c80bbbe -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Ending Placer Task | Checksum: 99ceed10 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 +Ending Placer Task | Checksum: 101790dce -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1334.406 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 45 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1335.719 ; gain = 0.000 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1335.719 ; gain = 0.000 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1334.406 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.323 . Memory (MB): peak = 1335.719 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.097 . Memory (MB): peak = 1334.406 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file CPU9bits_io_placed.rpt -report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.130 . Memory (MB): peak = 1335.719 ; gain = 0.000 +report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1334.406 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1335.719 ; gain = 0.000 +report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1334.406 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' @@ -308,68 +306,68 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs -Checksum: PlaceDB: 7bcec753 ConstDB: 0 ShapeSum: 1e0025bd RouteDB: 0 +Checksum: PlaceDB: 2e37d8f5 ConstDB: 0 ShapeSum: d34134d9 RouteDB: 0 Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 16c615449 +Phase 1 Build RT Design | Checksum: 7ebb6ebf -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1486.191 ; gain = 150.473 -Post Restoration Checksum: NetGraph: 8cbcc684 NumContArr: dfa48dc5 Constraints: 0 Timing: 0 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1485.609 ; gain = 151.203 +Post Restoration Checksum: NetGraph: 10180109 NumContArr: 6ea36db6 Constraints: 0 Timing: 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 16c615449 +Phase 2.1 Fix Topology Constraints | Checksum: 7ebb6ebf -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1490.352 ; gain = 154.633 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1489.359 ; gain = 154.953 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 16c615449 +Phase 2.2 Pre Route Cleanup | Checksum: 7ebb6ebf -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1490.352 ; gain = 154.633 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1489.359 ; gain = 154.953 Number of Nodes with overlaps = 0 -Phase 2 Router Initialization | Checksum: 10053be5d +Phase 2 Router Initialization | Checksum: dbaddab7 -Time (s): cpu = 00:00:50 ; elapsed = 00:00:39 . Memory (MB): peak = 1517.723 ; gain = 182.004 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 94ab7af4 +Phase 3 Initial Routing | Checksum: ad0f318a -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 15 + Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 -Phase 4.1 Global Iteration 0 | Checksum: ab64b9a3 +Phase 4.1 Global Iteration 0 | Checksum: 1246629fb -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 -Phase 4 Rip-up And Reroute | Checksum: ab64b9a3 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 +Phase 4 Rip-up And Reroute | Checksum: 1246629fb -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: ab64b9a3 +Phase 5 Delay and Skew Optimization | Checksum: 1246629fb -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: ab64b9a3 +Phase 6.1 Hold Fix Iter | Checksum: 1246629fb -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 -Phase 6 Post Hold Fix | Checksum: ab64b9a3 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 +Phase 6 Post Hold Fix | Checksum: 1246629fb -Time (s): cpu = 00:00:51 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 0.00626714 % - Global Horizontal Routing Utilization = 0.0102302 % + Global Vertical Routing Utilization = 0.00477869 % + Global Horizontal Routing Utilization = 0.00797101 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -379,10 +377,10 @@ Router Utilization Summary Number of Node Overlaps = 0 Congestion Report -North Dir 1x1 Area, Max Cong = 18.9189%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 10.8108%, No Congested Regions. -East Dir 1x1 Area, Max Cong = 22.0588%, No Congested Regions. -West Dir 1x1 Area, Max Cong = 27.9412%, No Congested Regions. +North Dir 1x1 Area, Max Cong = 9.00901%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 13.5135%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 16.1765%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 14.7059%, No Congested Regions. ------------------------------ Reporting congestion hotspots @@ -404,50 +402,50 @@ Direction: West Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Phase 7 Route finalize | Checksum: ab64b9a3 +Phase 7 Route finalize | Checksum: 1246629fb -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: ab64b9a3 +Phase 8 Verifying routed nets | Checksum: 1246629fb -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 148b7f565 +Phase 9 Depositing Routes | Checksum: 1219f5402 -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:52 ; elapsed = 00:00:40 . Memory (MB): peak = 1517.723 ; gain = 182.004 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:22 . Memory (MB): peak = 1516.082 ; gain = 181.676 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 57 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:56 ; elapsed = 00:00:42 . Memory (MB): peak = 1517.723 ; gain = 182.004 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1517.723 ; gain = 0.000 +route_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1516.082 ; gain = 181.676 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1516.082 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 1517.723 ; gain = 0.000 -INFO: [Common 17-1381] The checkpoint 'C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated. +Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1516.082 ; gain = 0.000 +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx Command: report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt. +INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt. report_drc completed successfully INFO: [runtcl-4] Executing : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx Command: report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads -INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/REPOSITORIES/Educational/Western Michigan University/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt. +INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt. report_methodology completed successfully INFO: [runtcl-4] Executing : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx Command: report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx @@ -470,4 +468,4 @@ INFO: [runtcl-4] Executing : report_clock_utilization -file CPU9bits_clock_utili INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs -INFO: [Common 17-206] Exiting Vivado at Sat Mar 30 15:55:20 2019... +INFO: [Common 17-206] Exiting Vivado at Sat Apr 6 17:35:04 2019... diff --git a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt index dad6504..1253210 100644 --- a/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_bus_skew_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:20 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) +| Date : Sat Apr 6 17:35:04 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_bus_skew -warn_on_violation -file CPU9bits_bus_skew_routed.rpt -pb CPU9bits_bus_skew_routed.pb -rpx CPU9bits_bus_skew_routed.rpx | Design : CPU9bits | Device : 7k160ti-fbg484 diff --git a/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt index be7e934..7b65097 100644 --- a/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_clock_utilization_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:20 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) +| Date : Sat Apr 6 17:35:04 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_clock_utilization -file CPU9bits_clock_utilization_routed.rpt | Design : CPU9bits | Device : 7k160ti-fbg484 @@ -44,7 +44,7 @@ Table of Contents +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ -| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 22 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 59 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -72,7 +72,7 @@ Table of Contents +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | -| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 21 | 2800 | 14 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 58 | 2800 | 29 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | | X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | @@ -105,7 +105,7 @@ All Modules +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ -| g0 | BUFG/O | n/a | | | | 22 | 0 | 0 | 0 | clk_IBUF_BUFG | +| g0 | BUFG/O | n/a | | | | 59 | 0 | 0 | 0 | clk_IBUF_BUFG | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types @@ -119,7 +119,7 @@ All Modules | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | -| Y1 | 22 | 0 | +| Y1 | 59 | 0 | | Y0 | 0 | 0 | +----+-----+----+ @@ -130,7 +130,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ -| g0 | n/a | BUFG/O | None | 22 | 0 | 21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | +| g0 | n/a | BUFG/O | None | 59 | 0 | 58 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) diff --git a/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt index b20d0aa..9a4c667 100644 --- a/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_control_sets_placed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:32 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) +| Date : Sat Apr 6 17:34:31 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_control_sets -verbose -file CPU9bits_control_sets_placed.rpt | Design : CPU9bits | Device : xc7k160ti @@ -24,7 +24,7 @@ Table of Contents | Status | Count | +----------------------------------------------------------+-------+ | Number of unique control sets | 3 | -| Unused register locations in slices containing registers | 19 | +| Unused register locations in slices containing registers | 14 | +----------------------------------------------------------+-------+ @@ -34,8 +34,8 @@ Table of Contents +--------+--------------+ | Fanout | Control Sets | +--------+--------------+ -| 3 | 1 | | 9 | 2 | +| 16+ | 1 | +--------+--------------+ @@ -45,24 +45,24 @@ Table of Contents +--------------+-----------------------+------------------------+-----------------+--------------+ | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | +--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 3 | 1 | +| No | No | No | 0 | 0 | | No | No | Yes | 0 | 0 | -| No | Yes | No | 0 | 0 | +| No | Yes | No | 40 | 11 | | Yes | No | No | 0 | 0 | | Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 18 | 8 | +| Yes | Yes | No | 18 | 6 | +--------------+-----------------------+------------------------+-----------------+--------------+ 4. Detailed Control Set Information ----------------------------------- -+----------------+----------------------------+------------------+------------------+----------------+ -| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | -+----------------+----------------------------+------------------+------------------+----------------+ -| clk_IBUF_BUFG | | | 1 | 3 | -| clk_IBUF_BUFG | FetchU/PC/E[0] | reset_IBUF | 4 | 9 | -| clk_IBUF_BUFG | FetchU/PC/Dout_reg[0]_1[0] | reset_IBUF | 4 | 9 | -+----------------+----------------------------+------------------+------------------+----------------+ ++----------------+------------------------+------------------+------------------+----------------+ +| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | ++----------------+------------------------+------------------+------------------+----------------+ +| clk_IBUF_BUFG | pipe2/E[0] | reset_IBUF | 3 | 9 | +| clk_IBUF_BUFG | pipe2/Dout_reg[5]_0[0] | reset_IBUF | 3 | 9 | +| clk_IBUF_BUFG | | reset_IBUF | 11 | 40 | ++----------------+------------------------+------------------+------------------+----------------+ diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt b/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt index df76f81..1a0055c 100644 --- a/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_drc_opted.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:22 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) +| Date : Sat Apr 6 17:34:27 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_drc -file CPU9bits_drc_opted.rpt -pb CPU9bits_drc_opted.pb -rpx CPU9bits_drc_opted.rpx | Design : CPU9bits | Device : xc7k160tifbg484-2L diff --git a/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt index cf64052..aaf378a 100644 --- a/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_drc_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:17 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) +| Date : Sat Apr 6 17:35:02 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_drc -file CPU9bits_drc_routed.rpt -pb CPU9bits_drc_routed.pb -rpx CPU9bits_drc_routed.rpx | Design : CPU9bits | Device : xc7k160tifbg484-2L diff --git a/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt index a4df712..c61aca3 100644 --- a/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_io_placed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:32 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) +| Date : Sat Apr 6 17:34:31 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_io -file CPU9bits_io_placed.rpt | Design : CPU9bits | Device : xc7k160ti diff --git a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb index 1cf5964..d40234b 100644 Binary files a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb and b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt index 82180e8..610c4ca 100644 --- a/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_methodology_drc_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:19 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) +| Date : Sat Apr 6 17:35:03 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx | Design : CPU9bits | Device : xc7k160tifbg484-2L @@ -23,123 +23,308 @@ Table of Contents Floorplan: design_1 Design limits: Max violations: - Violations found: 22 + Violations found: 59 +-----------+----------+-----------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+-----------------------------+------------+ -| TIMING-17 | Warning | Non-clocked sequential cell | 22 | +| TIMING-17 | Warning | Non-clocked sequential cell | 59 | +-----------+----------+-----------------------------+------------+ 2. REPORT DETAILS ----------------- TIMING-17#1 Warning Non-clocked sequential cell -The clock pin FetchU/PC/Dout_reg[0]/C is not reached by a timing clock +The clock pin EM/dM/memory_reg/CLKARDCLK is not reached by a timing clock Related violations: TIMING-17#2 Warning Non-clocked sequential cell -The clock pin FetchU/PC/Dout_reg[1]/C is not reached by a timing clock +The clock pin FD/FetchU/PC/Dout_reg[0]/C is not reached by a timing clock Related violations: TIMING-17#3 Warning Non-clocked sequential cell -The clock pin FetchU/PC/Dout_reg[2]/C is not reached by a timing clock +The clock pin FD/FetchU/PC/Dout_reg[1]/C is not reached by a timing clock Related violations: TIMING-17#4 Warning Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[0]/C is not reached by a timing clock +The clock pin FD/FetchU/PC/Dout_reg[2]/C is not reached by a timing clock Related violations: TIMING-17#5 Warning Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[1]/C is not reached by a timing clock +The clock pin FD/RF/r0/Dout_reg[0]/C is not reached by a timing clock Related violations: TIMING-17#6 Warning Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[2]/C is not reached by a timing clock +The clock pin FD/RF/r0/Dout_reg[1]/C is not reached by a timing clock Related violations: TIMING-17#7 Warning Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[3]/C is not reached by a timing clock +The clock pin FD/RF/r0/Dout_reg[2]/C is not reached by a timing clock Related violations: TIMING-17#8 Warning Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[4]/C is not reached by a timing clock +The clock pin FD/RF/r0/Dout_reg[3]/C is not reached by a timing clock Related violations: TIMING-17#9 Warning Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[5]/C is not reached by a timing clock +The clock pin FD/RF/r0/Dout_reg[4]/C is not reached by a timing clock Related violations: TIMING-17#10 Warning Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[6]/C is not reached by a timing clock +The clock pin FD/RF/r0/Dout_reg[5]/C is not reached by a timing clock Related violations: TIMING-17#11 Warning Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[7]/C is not reached by a timing clock +The clock pin FD/RF/r0/Dout_reg[6]/C is not reached by a timing clock Related violations: TIMING-17#12 Warning Non-clocked sequential cell -The clock pin RF/r0/Dout_reg[8]/C is not reached by a timing clock +The clock pin FD/RF/r0/Dout_reg[7]/C is not reached by a timing clock Related violations: TIMING-17#13 Warning Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[0]/C is not reached by a timing clock +The clock pin FD/RF/r0/Dout_reg[8]/C is not reached by a timing clock Related violations: TIMING-17#14 Warning Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[1]/C is not reached by a timing clock +The clock pin FD/RF/r1/Dout_reg[0]/C is not reached by a timing clock Related violations: TIMING-17#15 Warning Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[2]/C is not reached by a timing clock +The clock pin FD/RF/r1/Dout_reg[1]/C is not reached by a timing clock Related violations: TIMING-17#16 Warning Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[3]/C is not reached by a timing clock +The clock pin FD/RF/r1/Dout_reg[2]/C is not reached by a timing clock Related violations: TIMING-17#17 Warning Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[4]/C is not reached by a timing clock +The clock pin FD/RF/r1/Dout_reg[3]/C is not reached by a timing clock Related violations: TIMING-17#18 Warning Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[5]/C is not reached by a timing clock +The clock pin FD/RF/r1/Dout_reg[4]/C is not reached by a timing clock Related violations: TIMING-17#19 Warning Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[6]/C is not reached by a timing clock +The clock pin FD/RF/r1/Dout_reg[5]/C is not reached by a timing clock Related violations: TIMING-17#20 Warning Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[7]/C is not reached by a timing clock +The clock pin FD/RF/r1/Dout_reg[6]/C is not reached by a timing clock Related violations: TIMING-17#21 Warning Non-clocked sequential cell -The clock pin RF/r1/Dout_reg[8]/C is not reached by a timing clock +The clock pin FD/RF/r1/Dout_reg[7]/C is not reached by a timing clock Related violations: TIMING-17#22 Warning Non-clocked sequential cell -The clock pin dM/memory_reg/CLKARDCLK is not reached by a timing clock +The clock pin FD/RF/r1/Dout_reg[8]/C is not reached by a timing clock +Related violations: + +TIMING-17#23 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[12]/C is not reached by a timing clock +Related violations: + +TIMING-17#24 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[24]/C is not reached by a timing clock +Related violations: + +TIMING-17#25 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#26 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#27 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#28 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#29 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#30 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[2]/C is not reached by a timing clock +Related violations: + +TIMING-17#31 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#32 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#33 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[32]/C is not reached by a timing clock +Related violations: + +TIMING-17#34 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[33]/C is not reached by a timing clock +Related violations: + +TIMING-17#35 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[34]/C is not reached by a timing clock +Related violations: + +TIMING-17#36 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[35]/C is not reached by a timing clock +Related violations: + +TIMING-17#37 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[36]/C is not reached by a timing clock +Related violations: + +TIMING-17#38 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[37]/C is not reached by a timing clock +Related violations: + +TIMING-17#39 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[38]/C is not reached by a timing clock +Related violations: + +TIMING-17#40 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[39]/C is not reached by a timing clock +Related violations: + +TIMING-17#41 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[40]/C is not reached by a timing clock +Related violations: + +TIMING-17#42 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[41]/C is not reached by a timing clock +Related violations: + +TIMING-17#43 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[45]/C is not reached by a timing clock +Related violations: + +TIMING-17#44 Warning +Non-clocked sequential cell +The clock pin pipe1/Dout_reg[7]/C is not reached by a timing clock +Related violations: + +TIMING-17#45 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[0]/C is not reached by a timing clock +Related violations: + +TIMING-17#46 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[25]/C is not reached by a timing clock +Related violations: + +TIMING-17#47 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[26]/C is not reached by a timing clock +Related violations: + +TIMING-17#48 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[27]/C is not reached by a timing clock +Related violations: + +TIMING-17#49 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[28]/C is not reached by a timing clock +Related violations: + +TIMING-17#50 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[29]/C is not reached by a timing clock +Related violations: + +TIMING-17#51 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[30]/C is not reached by a timing clock +Related violations: + +TIMING-17#52 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[31]/C is not reached by a timing clock +Related violations: + +TIMING-17#53 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[32]/C is not reached by a timing clock +Related violations: + +TIMING-17#54 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[33]/C is not reached by a timing clock +Related violations: + +TIMING-17#55 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[34]/C is not reached by a timing clock +Related violations: + +TIMING-17#56 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[35]/C is not reached by a timing clock +Related violations: + +TIMING-17#57 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[36]/C is not reached by a timing clock +Related violations: + +TIMING-17#58 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[3]/C is not reached by a timing clock +Related violations: + +TIMING-17#59 Warning +Non-clocked sequential cell +The clock pin pipe2/Dout_reg[5]/C is not reached by a timing clock Related violations: diff --git a/lab2CA.runs/impl_1/CPU9bits_opt.dcp b/lab2CA.runs/impl_1/CPU9bits_opt.dcp index acc9d4f..369b44c 100644 Binary files a/lab2CA.runs/impl_1/CPU9bits_opt.dcp and b/lab2CA.runs/impl_1/CPU9bits_opt.dcp differ diff --git a/lab2CA.runs/impl_1/CPU9bits_placed.dcp b/lab2CA.runs/impl_1/CPU9bits_placed.dcp index 5677e49..e1f21b9 100644 Binary files a/lab2CA.runs/impl_1/CPU9bits_placed.dcp and b/lab2CA.runs/impl_1/CPU9bits_placed.dcp differ diff --git a/lab2CA.runs/impl_1/CPU9bits_power_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_power_routed.rpt index 42a27a1..1783114 100644 --- a/lab2CA.runs/impl_1/CPU9bits_power_routed.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_power_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:20 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) +| Date : Sat Apr 6 17:35:04 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx | Design : CPU9bits | Device : xc7k160tifbg484-2L @@ -30,14 +30,14 @@ Table of Contents ---------- +--------------------------+--------------+ -| Total On-Chip Power (W) | 11.172 | +| Total On-Chip Power (W) | 10.632 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 11.030 | -| Device Static (W) | 0.142 | +| Dynamic (W) | 10.494 | +| Device Static (W) | 0.137 | | Effective TJA (C/W) | 2.5 | -| Max Ambient (C) | 72.4 | -| Junction Temperature (C) | 52.6 | +| Max Ambient (C) | 73.7 | +| Junction Temperature (C) | 51.3 | | Confidence Level | Low | | Setting File | --- | | Simulation Activity File | --- | @@ -52,16 +52,16 @@ Table of Contents +----------------+-----------+----------+-----------+-----------------+ | On-Chip | Power (W) | Used | Available | Utilization (%) | +----------------+-----------+----------+-----------+-----------------+ -| Slice Logic | 1.248 | 107 | --- | --- | -| LUT as Logic | 1.231 | 73 | 101400 | 0.07 | -| Register | 0.012 | 21 | 202800 | 0.01 | +| Slice Logic | 0.768 | 132 | --- | --- | +| LUT as Logic | 0.719 | 54 | 101400 | 0.05 | +| Register | 0.043 | 58 | 202800 | 0.03 | | BUFG | 0.005 | 1 | 32 | 3.13 | -| Others | 0.000 | 4 | --- | --- | -| Signals | 1.328 | 114 | --- | --- | +| Others | 0.000 | 5 | --- | --- | +| Signals | 0.881 | 109 | --- | --- | | Block RAM | 0.060 | 0.5 | 325 | 0.15 | -| I/O | 8.393 | 12 | 285 | 4.21 | -| Static Power | 0.142 | | | | -| Total | 11.172 | | | | +| I/O | 8.785 | 12 | 285 | 4.21 | +| Static Power | 0.137 | | | | +| Total | 10.632 | | | | +----------------+-----------+----------+-----------+-----------------+ @@ -71,16 +71,16 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | +-----------+-------------+-----------+-------------+------------+ -| Vccint | 0.950 | 2.849 | 2.775 | 0.074 | -| Vccaux | 1.800 | 0.707 | 0.687 | 0.020 | +| Vccint | 0.950 | 1.868 | 1.799 | 0.070 | +| Vccaux | 1.800 | 0.738 | 0.719 | 0.020 | | Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | -| Vcco18 | 1.800 | 3.975 | 3.974 | 0.001 | +| Vcco18 | 1.800 | 4.161 | 4.160 | 0.001 | | Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | | Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | | Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | | Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | -| Vccbram | 0.950 | 0.007 | 0.005 | 0.002 | +| Vccbram | 0.950 | 0.006 | 0.005 | 0.002 | | MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | | MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | | MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | @@ -136,16 +136,22 @@ Table of Contents 3.1 By Hierarchy ---------------- -+----------+-----------+ -| Name | Power (W) | -+----------+-----------+ -| CPU9bits | 11.030 | -| FetchU | 1.191 | -| PC | 1.191 | -| RF | 1.317 | -| r0 | 0.812 | -| r1 | 0.506 | -| dM | 0.113 | -+----------+-----------+ ++------------+-----------+ +| Name | Power (W) | ++------------+-----------+ +| CPU9bits | 10.494 | +| EM | 0.099 | +| dM | 0.099 | +| FD | 0.424 | +| FetchU | 0.179 | +| PC | 0.179 | +| RF | 0.244 | +| r0 | 0.133 | +| r1 | 0.112 | +| W | 0.301 | +| mux5 | 0.301 | +| pipe1 | 0.782 | +| pipe2 | 0.087 | ++------------+-----------+ diff --git a/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb b/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb index f938afd..9ffa97b 100644 Binary files a/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb and b/lab2CA.runs/impl_1/CPU9bits_power_summary_routed.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_route_status.pb b/lab2CA.runs/impl_1/CPU9bits_route_status.pb index a8cf179..8c3ca07 100644 Binary files a/lab2CA.runs/impl_1/CPU9bits_route_status.pb and b/lab2CA.runs/impl_1/CPU9bits_route_status.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_route_status.rpt b/lab2CA.runs/impl_1/CPU9bits_route_status.rpt index 368950c..b33440b 100644 --- a/lab2CA.runs/impl_1/CPU9bits_route_status.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_route_status.rpt @@ -1,11 +1,11 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 128 : - # of nets not needing routing.......... : 12 : - # of internally routed nets........ : 12 : - # of routable nets..................... : 116 : - # of fully routed nets............. : 116 : + # of logical nets.......................... : 152 : + # of nets not needing routing.......... : 41 : + # of internally routed nets........ : 41 : + # of routable nets..................... : 111 : + # of fully routed nets............. : 111 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/lab2CA.runs/impl_1/CPU9bits_routed.dcp b/lab2CA.runs/impl_1/CPU9bits_routed.dcp index 736cead..bc07617 100644 Binary files a/lab2CA.runs/impl_1/CPU9bits_routed.dcp and b/lab2CA.runs/impl_1/CPU9bits_routed.dcp differ diff --git a/lab2CA.runs/impl_1/CPU9bits_tb.vdi b/lab2CA.runs/impl_1/CPU9bits_tb.vdi deleted file mode 100644 index b2588e7..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_tb.vdi +++ /dev/null @@ -1,173 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sun Mar 24 18:38:44 2019 -# Process ID: 13064 -# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1 -# Command line: vivado.exe -log CPU9bits_tb.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU9bits_tb.tcl -notrace -# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb.vdi -# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1\vivado.jou -#----------------------------------------------------------- -source CPU9bits_tb.tcl -notrace -Command: link_design -top CPU9bits_tb -part xc7k160tifbg484-2L -Design is defaulting to srcset: sources_1 -Design is defaulting to constrset: constrs_1 -INFO: [Project 1-479] Netlist was created with Vivado 2018.3 -INFO: [Device 21-403] Loading part xc7k160tifbg484-2L -INFO: [Project 1-570] Preparing netlist for logic optimization -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 579.477 ; gain = 0.000 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -link_design completed successfully -link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 579.477 ; gain = 327.758 -Command: opt_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' -Running DRC as a precondition to command opt_design - -Starting DRC Task -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Project 1-461] DRC finished with 0 Errors -INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 583.891 ; gain = 4.082 - -Starting Cache Timing Information Task -INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: f67b9b0d - -Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1077.012 ; gain = 493.121 - -Starting Logic Optimization Task - -Phase 1 Retarget -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: f67b9b0d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells - -Phase 2 Constant propagation -INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells - -Phase 3 Sweep -Phase 3 Sweep | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells - -Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.024 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. - -Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.059 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells - -Phase 6 Post Processing Netlist -Phase 6 Post Processing Netlist | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells -Opt_design Change Summary -========================= - - -------------------------------------------------------------------------------------------------------------------------- -| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | -------------------------------------------------------------------------------------------------------------------------- -| Retarget | 0 | 0 | 0 | -| Constant propagation | 0 | 0 | 0 | -| Sweep | 0 | 0 | 0 | -| BUFG optimization | 0 | 0 | 0 | -| Shift Register Optimization | 0 | 0 | 0 | -| Post Processing Netlist | 0 | 0 | 0 | -------------------------------------------------------------------------------------------------------------------------- - - - -Starting Connectivity Check Task - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 -Ending Logic Optimization Task | Checksum: f67b9b0d - -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.062 . Memory (MB): peak = 1167.297 ; gain = 0.000 - -Starting Power Optimization Task -INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: f67b9b0d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1167.297 ; gain = 0.000 - -Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: f67b9b0d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 - -Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 -Ending Netlist Obfuscation Task | Checksum: f67b9b0d - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 -INFO: [Common 17-83] Releasing license: Implementation -20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. -opt_design completed successfully -opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1167.297 ; gain = 587.559 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1167.297 ; gain = 0.000 -WARNING: [Constraints 18-5210] No constraints selected for write. -Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. -INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp' has been generated. -INFO: [runtcl-4] Executing : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx -Command: report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx -INFO: [IP_Flow 19-234] Refreshing IP repositories -INFO: [IP_Flow 19-1704] No user IP repositories specified -INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt. -report_drc completed successfully -Command: place_design -Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. -Running DRC as a precondition to command place_design -INFO: [DRC 23-27] Running DRC with 2 threads -INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors -INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. - -Starting Placer Task -INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs - -Phase 1 Placer Initialization - -Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1192.641 ; gain = 0.000 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1192.641 ; gain = 0.328 -Phase 1 Placer Initialization | Checksum: 00000000 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1192.641 ; gain = 0.328 -ERROR: [Place 30-494] The design is empty -Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports. -Ending Placer Task | Checksum: 00000000 - -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1192.641 ; gain = 0.328 -INFO: [Common 17-83] Releasing license: Implementation -36 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered. -place_design failed -ERROR: [Common 17-69] Command failed: Placer could not place all instances -INFO: [Common 17-206] Exiting Vivado at Sun Mar 24 18:39:16 2019... diff --git a/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb b/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb deleted file mode 100644 index 70698d1..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.pb and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt b/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt deleted file mode 100644 index f3fdc2b..0000000 --- a/lab2CA.runs/impl_1/CPU9bits_tb_drc_opted.rpt +++ /dev/null @@ -1,49 +0,0 @@ -Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------- -| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sun Mar 24 18:39:15 2019 -| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) -| Command : report_drc -file CPU9bits_tb_drc_opted.rpt -pb CPU9bits_tb_drc_opted.pb -rpx CPU9bits_tb_drc_opted.rpx -| Design : CPU9bits_tb -| Device : xc7k160tifbg484-2L -| Speed File : -2L -| Design State : Fully Routed ------------------------------------------------------------------------------------------------------------------------- - -Report DRC - -Table of Contents ------------------ -1. REPORT SUMMARY -2. REPORT DETAILS - -1. REPORT SUMMARY ------------------ - Netlist: netlist - Floorplan: design_1 - Design limits: - Ruledeck: default - Max violations: - Violations found: 1 -+----------+----------+-----------------------------------------------------+------------+ -| Rule | Severity | Description | Violations | -+----------+----------+-----------------------------------------------------+------------+ -| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 | -+----------+----------+-----------------------------------------------------+------------+ - -2. REPORT DETAILS ------------------ -CFGBVS-1#1 Warning -Missing CFGBVS and CONFIG_VOLTAGE Design Properties -Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: - - set_property CFGBVS value1 [current_design] - #where value1 is either VCCO or GND - - set_property CONFIG_VOLTAGE value2 [current_design] - #where value2 is the voltage provided to configuration bank 0 - -Refer to the device configuration user guide for more information. -Related violations: - - diff --git a/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp b/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp deleted file mode 100644 index a888ad7..0000000 Binary files a/lab2CA.runs/impl_1/CPU9bits_tb_opt.dcp and /dev/null differ diff --git a/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt b/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt index 606f9c2..b0b9c67 100644 --- a/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_timing_summary_routed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:55:20 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) +| Date : Sat Apr 6 17:35:04 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -file CPU9bits_timing_summary_routed.rpt -pb CPU9bits_timing_summary_routed.pb -rpx CPU9bits_timing_summary_routed.rpx -warn_on_violation | Design : CPU9bits | Device : 7k160ti-fbg484 @@ -52,7 +52,7 @@ Table of Contents 1. checking no_clock -------------------- - There are 22 register/latch pins with no clock driven by root clock pin: clk (HIGH) + There are 59 register/latch pins with no clock driven by root clock pin: clk (HIGH) 2. checking constant_clock @@ -67,7 +67,7 @@ Table of Contents 4. checking unconstrained_internal_endpoints -------------------------------------------- - There are 75 pins that are not constrained for maximum delay. (HIGH) + There are 152 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. diff --git a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb index 0e56dc6..c2cf86b 100644 Binary files a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb and b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.pb differ diff --git a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt index e85b036..0b2ed7b 100644 --- a/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt +++ b/lab2CA.runs/impl_1/CPU9bits_utilization_placed.rpt @@ -1,8 +1,8 @@ Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -| Date : Sat Mar 30 15:54:32 2019 -| Host : WM-G75VW running 64-bit major release (build 9200) +| Date : Sat Apr 6 17:34:31 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_utilization -file CPU9bits_utilization_placed.rpt -pb CPU9bits_utilization_placed.pb | Design : CPU9bits | Device : 7k160tifbg484-2L @@ -31,11 +31,11 @@ Table of Contents +-------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------+------+-------+-----------+-------+ -| Slice LUTs | 73 | 0 | 101400 | 0.07 | -| LUT as Logic | 73 | 0 | 101400 | 0.07 | +| Slice LUTs | 54 | 0 | 101400 | 0.05 | +| LUT as Logic | 54 | 0 | 101400 | 0.05 | | LUT as Memory | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 21 | 0 | 202800 | 0.01 | -| Register as Flip Flop | 21 | 0 | 202800 | 0.01 | +| Slice Registers | 58 | 0 | 202800 | 0.03 | +| Register as Flip Flop | 58 | 0 | 202800 | 0.03 | | Register as Latch | 0 | 0 | 202800 | 0.00 | | F7 Muxes | 0 | 0 | 50700 | 0.00 | | F8 Muxes | 0 | 0 | 25350 | 0.00 | @@ -57,7 +57,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 21 | Yes | Reset | - | +| 58 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -68,20 +68,20 @@ Table of Contents | Site Type | Used | Fixed | Available | Util% | +--------------------------------------------+------+-------+-----------+-------+ | Slice | 21 | 0 | 25350 | 0.08 | -| SLICEL | 11 | 0 | | | -| SLICEM | 10 | 0 | | | -| LUT as Logic | 73 | 0 | 101400 | 0.07 | +| SLICEL | 12 | 0 | | | +| SLICEM | 9 | 0 | | | +| LUT as Logic | 54 | 0 | 101400 | 0.05 | | using O5 output only | 0 | | | | -| using O6 output only | 65 | | | | -| using O5 and O6 | 8 | | | | +| using O6 output only | 40 | | | | +| using O5 and O6 | 14 | | | | | LUT as Memory | 0 | 0 | 35000 | 0.00 | | LUT as Distributed RAM | 0 | 0 | | | | LUT as Shift Register | 0 | 0 | | | -| Slice Registers | 21 | 0 | 202800 | 0.01 | -| Register driven from within the Slice | 4 | | | | -| Register driven from outside the Slice | 17 | | | | -| LUT in front of the register is unused | 0 | | | | -| LUT in front of the register is used | 17 | | | | +| Slice Registers | 58 | 0 | 202800 | 0.03 | +| Register driven from within the Slice | 34 | | | | +| Register driven from outside the Slice | 24 | | | | +| LUT in front of the register is unused | 17 | | | | +| LUT in front of the register is used | 7 | | | | | Unique Control Sets | 3 | | 25350 | 0.01 | +--------------------------------------------+------+-------+-----------+-------+ * Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. @@ -180,15 +180,16 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| LUT6 | 37 | LUT | -| LUT4 | 27 | LUT | -| FDRE | 21 | Flop & Latch | +| FDRE | 58 | Flop & Latch | +| LUT4 | 23 | LUT | +| LUT3 | 18 | LUT | +| LUT5 | 11 | LUT | | OBUF | 10 | IO | -| LUT5 | 10 | LUT | -| LUT2 | 4 | LUT | -| LUT3 | 3 | LUT | +| LUT6 | 9 | LUT | +| LUT2 | 6 | LUT | | IBUF | 2 | IO | | RAMB18E1 | 1 | Block Memory | +| LUT1 | 1 | LUT | | BUFG | 1 | Clock | +----------+------+---------------------+ diff --git a/lab2CA.runs/impl_1/gen_run.xml b/lab2CA.runs/impl_1/gen_run.xml index fdb8b46..f988e68 100644 --- a/lab2CA.runs/impl_1/gen_run.xml +++ b/lab2CA.runs/impl_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -92,6 +92,20 @@ + + + + + + + + + + + + + + @@ -106,6 +120,13 @@ + + + + + + + @@ -135,6 +156,14 @@ + + + + + + + +