diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml
index 6b83595..44d18d6 100644
--- a/lab2CA.runs/synth_1/gen_run.xml
+++ b/lab2CA.runs/synth_1/gen_run.xml
@@ -4,8 +4,6 @@
-
-
diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v
index f1f476a..4370394 100644
--- a/lab2CA.srcs/sources_1/new/BasicModules.v
+++ b/lab2CA.srcs/sources_1/new/BasicModules.v
@@ -850,6 +850,40 @@ module register_tb();
end
endmodule
+module fDPipReg(
+ input wire clk,
+ input wire reset,
+ input wire En,
+ input wire [42:0] Din,
+ output reg [42:0] Dout);
+
+ always @(posedge clk) begin
+ if (reset == 1'b1) begin
+ Dout <= 23'b0000;
+ end
+ else if (En == 1'b0) begin
+ Dout <= Din;
+ end
+ end
+endmodule
+
+module eMPipReg(
+ input wire clk,
+ input wire reset,
+ input wire En,
+ input wire [42:0] Din,
+ output reg [42:0] Dout);
+
+ always @(posedge clk) begin
+ if (reset == 1'b1) begin
+ Dout <= 23'b0000;
+ end
+ else if (En == 1'b0) begin
+ Dout <= Din;
+ end
+ end
+endmodule
+
module shift_left(
input wire [7:0] A,
output wire [8:0] B);