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BEQ and LD fix

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This commit is contained in:
Johannes
2019-03-24 16:05:16 -04:00
parent 27f6d24b88
commit e8ada91e08
12 changed files with 193 additions and 131 deletions
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10
lab2CA.srcs/sources_1/new/CPU9bits.v
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@@ -9,7 +9,7 @@ module CPU9bits(
wire [2:0] FU;
wire [3:0] aluOp;
wire [1:0] bankS;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js;
wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;
instructionMemory iM(
.clk(clk),
@@ -19,7 +19,7 @@ module CPU9bits(
dataMemory dM(
.clk(clk),
.writeEnable(loadS),
.writeEnable(dataMemEn),
.writeData(op0),
.address(op1),
.readData(dataMemOut)
@@ -71,6 +71,7 @@ module CPU9bits(
.FU(FU),
.addi(addiS),
.mem(loadS),
.dataMemEn(dataMemEn),
.RegEn(RegEn),
.halt(done),
.link(link),
@@ -117,7 +118,7 @@ module CPU9bits(
bit1_mux_2_1 BranMux( // BEQ MUX
.A(FU[0]),
.B(op0[0]),
.B(AluOut[0]),
.out(fetchBranch),
.switch(FU[2])); // FU[2] only goes high when BEQ
@@ -185,8 +186,9 @@ module CPU9bits_tb();
.done(done));
initial begin
#10
reset = 1'b1;
#15
#10
reset = 1'b0;
#500

21
lab2CA.srcs/sources_1/new/ControlUnit.v
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@@ -6,7 +6,7 @@ module ControlUnit(
output reg [3:0] aluOut,
output reg [2:0] FU,
output reg addi,
output reg mem,
output reg mem, dataMemEn,
output reg RegEn,
output reg halt,
output reg link,
@@ -23,6 +23,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -34,6 +35,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -45,6 +47,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -56,6 +59,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -68,6 +72,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -79,6 +84,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -91,6 +97,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -102,6 +109,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -113,6 +121,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -124,6 +133,7 @@ module ControlUnit(
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -135,6 +145,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -146,6 +157,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
@@ -157,17 +169,19 @@ module ControlUnit(
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
end
4'b1100: begin
aluOut <= 4'b0000;
aluOut <= 4'b1010;
FU <= 3'b110; // branch
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -179,6 +193,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -186,6 +201,7 @@ module ControlUnit(
4'b0001: begin
aluOut <= 4'b0000;
mem <= 1'b1; // load
dataMemEn <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
@@ -197,6 +213,7 @@ module ControlUnit(
4'b0010: begin
aluOut <= 4'b0000;
mem <= 1'b0; // store
dataMemEn <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;

2
lab2CA.srcs/sources_1/new/dataMemory.v
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@@ -31,7 +31,7 @@ module dataMemory(
always@(address, clk, memory)begin
if(clk == 1'b1)begin
readData <= memory[address];
if(writeEnable == 1'b0)begin
if(writeEnable == 1'b1)begin
memory[address] <= writeData;
end
else begin

4
lab2CA.srcs/sources_1/new/instructionMemory.v
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@@ -28,7 +28,7 @@ module instructionMemory(
// memory[13] <= 9'b111111001; //srl
// // memory[14] <= 9'b100100010; //j
// memory[14] <= 9'b010001000; //zero
// memory[15] <= 9'b110001101; //beq
// memory[15] <= 9'b110001001; //beq
// memory[16] <= 9'b100001000; //jr
// memory[17] <= 9'b100111100; //j
@@ -48,7 +48,7 @@ module instructionMemory(
memory[11] <= 9'b000111110;
memory[12] <= 9'b101010000;
memory[13] <= 9'b101000010;
memory[14] <= 9'b101010100;
memory[14] <= 9'b101001100;
memory[15] <= 9'b101011110; //ends initialization
memory[16] <= 9'b101000011;
memory[17] <= 9'b101001101;