BEQ and LD fix

lab2CA.srcs/sources_1/new/CPU9bits.v

@@ -9,7 +9,7 @@ module CPU9bits(
     wire [2:0] FU;
     wire [3:0] aluOp;
     wire [1:0] bankS;
-    wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js;
+    wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;
         
     instructionMemory iM(
         .clk(clk),
@@ -19,7 +19,7 @@ module CPU9bits(
     
     dataMemory dM(
         .clk(clk),
-        .writeEnable(loadS),
+        .writeEnable(dataMemEn),
         .writeData(op0),
         .address(op1),
         .readData(dataMemOut)
@@ -71,6 +71,7 @@ module CPU9bits(
         .FU(FU),
         .addi(addiS),
         .mem(loadS),
+        .dataMemEn(dataMemEn),
         .RegEn(RegEn),
         .halt(done),
         .link(link),
@@ -117,7 +118,7 @@ module CPU9bits(
             
     bit1_mux_2_1 BranMux( // BEQ MUX
         .A(FU[0]),
-        .B(op0[0]),
+        .B(AluOut[0]),
         .out(fetchBranch),
         .switch(FU[2])); // FU[2] only goes high when BEQ
         
@@ -185,8 +186,9 @@ module CPU9bits_tb();
         .done(done));
         
     initial begin
+        #10
         reset = 1'b1;
-        #15
+        #10
         reset = 1'b0;
         #500