William/WMU-ECE-3570-Lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

BEQ and LD fix

Browse Source
This commit is contained in:
Johannes
2019-03-24 16:05:16 -04:00
parent 27f6d24b88
commit e8ada91e08
12 changed files with 193 additions and 131 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
lab2CA.srcs/sources_1/new/ControlUnit.v
View File

@@ -6,7 +6,7 @@ module ControlUnit(
output reg [3:0] aluOut,
output reg [2:0] FU,
output reg addi,
output reg mem,
output reg mem, dataMemEn,
output reg RegEn,
output reg halt,
output reg link,
@@ -23,6 +23,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -34,6 +35,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -45,6 +47,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -56,6 +59,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -68,6 +72,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -79,6 +84,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -91,6 +97,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -102,6 +109,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -113,6 +121,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -124,6 +133,7 @@ module ControlUnit(
FU <= 3'b001; // Disable Branching
halt <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -135,6 +145,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -146,6 +157,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b1;
@@ -157,17 +169,19 @@ module ControlUnit(
addi <= 1'b0;
aluOut <= 4'b0000;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b1;
bank <= 2'b10;
js <= 1'b0;
end
4'b1100: begin
aluOut <= 4'b0000;
aluOut <= 4'b1010;
FU <= 3'b110; // branch
RegEn <= 1'b1;
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -179,6 +193,7 @@ module ControlUnit(
halt <= 1'b0;
addi <= 1'b0;
mem <= 1'b0;
dataMemEn <= 1'b0;
link <= 1'b0;
bank <= 2'b10;
js <= 1'b0;
@@ -186,6 +201,7 @@ module ControlUnit(
4'b0001: begin
aluOut <= 4'b0000;
mem <= 1'b1; // load
dataMemEn <= 1'b0;
RegEn <= 1'b0;
FU <= 3'b001; // Disable Branching
addi <= 1'b0;
@@ -197,6 +213,7 @@ module ControlUnit(
4'b0010: begin
aluOut <= 4'b0000;
mem <= 1'b0; // store
dataMemEn <= 1'b1;
RegEn <= 1'b1;
FU <= 3'b001; // Disable Branching
halt <= 1'b0;