BEQ and LD fix

2019-03-24 16:05:16 -04:00
parent 27f6d24b88
commit e8ada91e08
12 changed files with 193 additions and 131 deletions
--- a/lab2CA.srcs/sources_1/new/dataMemory.v
+++ b/lab2CA.srcs/sources_1/new/dataMemory.v
@@ -31,7 +31,7 @@ module dataMemory(
    always@(address, clk, memory)begin
        if(clk == 1'b1)begin
        readData <= memory[address];
-        if(writeEnable == 1'b0)begin
+        if(writeEnable == 1'b1)begin
        memory[address] <= writeData;
        end
        else begin