diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index ea44869..2638199 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -34,7 +34,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -66,7 +66,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -88,12 +88,12 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -118,7 +118,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -153,7 +153,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -166,7 +166,7 @@ This means code written to parse this file will need to be revisited each subseq - + diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v index 9e163bc..8b6eae9 100644 --- a/lab2CA.srcs/sources_1/new/CPU9bits.v +++ b/lab2CA.srcs/sources_1/new/CPU9bits.v @@ -180,16 +180,12 @@ module CPU9bits( case(instr[8:5]) 4'b0001: // Load Byte result <= dataMemOut; - 4'b0011: // Link - result <= linkData; 4'b0101: // Add/Subtract result <= AluOut; 4'b0110: // Add Immediate result <= AddiOut; 4'b0111: // Set if Less Than result <= AluOut; - 4'b1010: // Bank Load/Bank Store - result <= RFIn; 4'b1101: // NOR result <= AluOut; 4'b1110: // OR/AND