diff --git a/Bank_behav1.wcfg b/Bank_behav1.wcfg
index 123f0ad..33afe34 100644
--- a/Bank_behav1.wcfg
+++ b/Bank_behav1.wcfg
@@ -11,9 +11,9 @@
-
-
-
+
+
+
@@ -39,6 +39,7 @@
address[8:0]
address[8:0]
+ UNSIGNEDDECRADIX
readData[8:0]
@@ -64,18 +65,22 @@
r0_out[8:0]
r0_out[8:0]
+ UNSIGNEDDECRADIX
r1_out[8:0]
r1_out[8:0]
+ UNSIGNEDDECRADIX
r2_out[8:0]
r2_out[8:0]
+ UNSIGNEDDECRADIX
r3_out[8:0]
r3_out[8:0]
+ UNSIGNEDDECRADIX
enable
@@ -100,6 +105,7 @@
r0_out[8:0]
r0_out[8:0]
+ UNSIGNEDDECRADIX
r1_out[8:0]
@@ -108,6 +114,7 @@
r2_out[8:0]
r2_out[8:0]
+ UNSIGNEDDECRADIX
r3_out[8:0]
@@ -120,6 +127,7 @@
AddrOut[8:0]
AddrOut[8:0]
+ UNSIGNEDDECRADIX
progC_out[8:0]
diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml
index 98ed877..852d7f4 100644
--- a/lab2CA.cache/wt/webtalk_pa.xml
+++ b/lab2CA.cache/wt/webtalk_pa.xml
@@ -3,7 +3,7 @@
-
+
@@ -17,7 +17,7 @@ This means code written to parse this file will need to be revisited each subseq
-
-
+
@@ -34,8 +34,8 @@ This means code written to parse this file will need to be revisited each subseq
-
-
+
+
@@ -46,7 +46,7 @@ This means code written to parse this file will need to be revisited each subseq
-
+
@@ -54,39 +54,40 @@ This means code written to parse this file will need to be revisited each subseq
-
+
-
+
+
-
+
-
-
+
+
-
+
-
+
-
+
-
+
@@ -110,7 +111,7 @@ This means code written to parse this file will need to be revisited each subseq
-
+
@@ -118,9 +119,9 @@ This means code written to parse this file will need to be revisited each subseq
-
+
-
+
@@ -129,16 +130,16 @@ This means code written to parse this file will need to be revisited each subseq
-
+
-
+
-
+
@@ -146,7 +147,7 @@ This means code written to parse this file will need to be revisited each subseq
-
+
@@ -159,20 +160,20 @@ This means code written to parse this file will need to be revisited each subseq
-
+
-
+
-
-
+
-
+
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
index ce99532..7530080 100644
--- a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
+++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/xsim_webtalk.tcl
@@ -1,6 +1,6 @@
webtalk_init -webtalk_dir C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/
webtalk_register_client -client project
-webtalk_add_data -client project -key date_generated -value "Sun Mar 24 16:34:26 2019" -context "software_version_and_target_device"
+webtalk_add_data -client project -key date_generated -value "Sun Mar 24 17:29:22 2019" -context "software_version_and_target_device"
webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device"
webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device"
@@ -14,7 +14,7 @@ webtalk_add_data -client project -key target_package -value "not_applicable" -co
webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device"
webtalk_add_data -client project -key random_id -value "17336daf-0d92-4f07-b4a4-ff1c52043edb" -context "software_version_and_target_device"
webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device"
-webtalk_add_data -client project -key project_iteration -value "82" -context "software_version_and_target_device"
+webtalk_add_data -client project -key project_iteration -value "98" -context "software_version_and_target_device"
webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment"
webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment"
webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz" -context "user_environment"
@@ -22,21 +22,11 @@ webtalk_add_data -client project -key cpu_speed -value "2594 MHz" -context "user
webtalk_add_data -client project -key total_processors -value "1" -context "user_environment"
webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment"
webtalk_register_client -client xsim
-webtalk_add_data -client xsim -key File_Counter -value "9" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key Command -value "xelab" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key Vhdl2008 -value "false" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key GenDLL -value "false" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key SDFModeling -value "false" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key HWCosim -value "false" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key DPI_Used -value "false" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key Debug -value "typical" -context "xsim\\command_line_options"
-webtalk_add_data -client xsim -key Simulation_Image_Code -value "109 KB" -context "xsim\\usage"
-webtalk_add_data -client xsim -key Simulation_Image_Data -value "19 KB" -context "xsim\\usage"
-webtalk_add_data -client xsim -key Total_Nets -value "0" -context "xsim\\usage"
-webtalk_add_data -client xsim -key Total_Processes -value "281" -context "xsim\\usage"
-webtalk_add_data -client xsim -key Total_Instances -value "144" -context "xsim\\usage"
-webtalk_add_data -client xsim -key Xilinx_HDL_Libraries_Used -value "secureip unimacro_ver unisims_ver " -context "xsim\\usage"
-webtalk_add_data -client xsim -key Compiler_Time -value "1.19_sec" -context "xsim\\usage"
-webtalk_add_data -client xsim -key Compiler_Memory -value "49056_KB" -context "xsim\\usage"
-webtalk_transmit -clientid 4125363012 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "XSIM Usage Report
"
+webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options"
+webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage"
+webtalk_add_data -client xsim -key runtime -value "520 ns" -context "xsim\\usage"
+webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage"
+webtalk_add_data -client xsim -key Simulation_Memory -value "5832_KB" -context "xsim\\usage"
+webtalk_transmit -clientid 567316716 -regid "" -xml C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/JoseIgnacio/CA Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "XSIM Usage Report
"
webtalk_terminate
diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem
index e0224a8..90fe9b6 100644
Binary files a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/CPU9bits_tb_behav/xsim.mem differ
diff --git a/lab2CA.srcs/sources_1/new/instructionMemory.v b/lab2CA.srcs/sources_1/new/instructionMemory.v
index e6210eb..58c6ac6 100644
--- a/lab2CA.srcs/sources_1/new/instructionMemory.v
+++ b/lab2CA.srcs/sources_1/new/instructionMemory.v
@@ -77,39 +77,38 @@ module instructionMemory(
// Binary Search
-
- memory[0] <= 9'b000000000;
+ memory[0] <= 9'b000000000;
memory[1] <= 9'b000000000;
memory[2] <= 9'b000000000;
memory[3] <= 9'b000000000;
memory[4] <= 9'b000000000;
- memory[5] <= 9'b000000000;
- memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)
+ memory[5] <= 9'b011001011; //addi R1, 3 (N = 3)
+ memory[6] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[7] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[8] <= 9'b011001011; //addi R1, 3 (N = 3)
memory[9] <= 9'b011001011; //addi R1, 3 (N = 3)
- memory[10] <= 9'b011001011; //addi R1, 3 (N = 3)
- memory[11] <= 9'b011010010; //addi R2, 2 (inputAddr = 2)
- memory[12] <= 9'b000111110; //lb R3, R3
- memory[13] <= 9'b101011010; //banks R3, 1
- memory[14] <= 9'b011001011; //addi R1, 3 (N = 3)
- memory[15] <= 9'b101000000; //loop: banks R0, 0
- memory[16] <= 9'b011100010; //slt R0, R1
- memory[17] <= 9'b110000001; //beq R0, Exit
- memory[18] <= 9'b100100001; //j Skip0
- memory[19] <= 9'b100101110; //Exit: j Loose
- memory[20] <= 9'b010101000; //Skip0: add R2, R0
- memory[21] <= 9'b010101010; //add R2, R1
- memory[22] <= 9'b111110000; //sll R2
+ memory[10] <= 9'b011011010; //addi R3, 2 (inputAddr = 2)
+ memory[11] <= 9'b000111110; //lb R3, R3
+ memory[12] <= 9'b101011010; //banks R3, 1
+ memory[13] <= 9'b011001011; //addi R1, 3 (N = 3)
+ memory[14] <= 9'b101000000; //loop: banks R0, 0
+ memory[15] <= 9'b011100010; //slt R0, R1
+ memory[16] <= 9'b110000001; //beq R0, Exit
+ memory[17] <= 9'b100100001; //j Skip0
+ memory[18] <= 9'b100101111; //Exit: j Loose
+ memory[19] <= 9'b101000001; //Skip0: bankl R0, 0
+ memory[20] <= 9'b010110000; //add R2, R0
+ memory[21] <= 9'b010110010; //add R2, R1
+ memory[22] <= 9'b111110001; //srl R2
memory[23] <= 9'b101011011; //bankl R3,1
memory[24] <= 9'b010111100; //add R3, R2
memory[25] <= 9'b101001100; //banks R1, 2
memory[26] <= 9'b000100110; //lb R0, R3
memory[27] <= 9'b010001000; //zero R1
- memory[28] <= 9'b011001010; //addi R1, 1 (numAddr = 1)
+ memory[28] <= 9'b011001001; //addi R1, 1 (numAddr = 1)
memory[29] <= 9'b000101010; //lb R1, R1
memory[30] <= 9'b100100001; //j SkipU
- memory[31] <= 9'b101110001; //j TransLoop
+ memory[31] <= 9'b101110010; //j TransLoop
memory[32] <= 9'b101010110; //SkipU: banks R2, 3
memory[33] <= 9'b100100001; //j SkipD
memory[34] <= 9'b100110111; //j TransLoose
@@ -122,10 +121,10 @@ module instructionMemory(
memory[41] <= 9'b010001000; //Skip1: zero R1
memory[42] <= 9'b010101100; //add R1, R2
memory[43] <= 9'b011100010; //slt R0, R1
- memory[44] <= 9'b110001001; //beq R1, Go2
+ memory[44] <= 9'b110000001; //beq R0, Go2
memory[45] <= 9'b100100110; //j Skip2
memory[46] <= 9'b010000000; //Go2: zero R0
- memory[47] <= 9'b011000010; //addi R0, 1
+ memory[47] <= 9'b011000001; //addi R0, 1
memory[48] <= 9'b101001111; //bankl R1,3
memory[49] <= 9'b010100010; //add R0, R1
memory[50] <= 9'b101001101; //bankl R1,2
diff --git a/lab2CA.xpr b/lab2CA.xpr
index 9a80179..64c236e 100644
--- a/lab2CA.xpr
+++ b/lab2CA.xpr
@@ -31,7 +31,7 @@
-
+