From f4b2ddebc126e9b905db3c00c1156dc3ccfa50a8 Mon Sep 17 00:00:00 2001
From: WilliamMiceli <git@williammiceli.me>
Date: Sat, 6 Apr 2019 14:17:10 -0400
Subject: [PATCH] Added back enable signals

---
 lab2CA.srcs/sources_1/new/CPU9bits.v | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lab2CA.srcs/sources_1/new/CPU9bits.v b/lab2CA.srcs/sources_1/new/CPU9bits.v
index e933368..5588f78 100644
--- a/lab2CA.srcs/sources_1/new/CPU9bits.v
+++ b/lab2CA.srcs/sources_1/new/CPU9bits.v
@@ -28,6 +28,7 @@ module CPU9bits(
     RegFile RF(
         .clk(clk),
         .reset(reset),
+        .enable(RegEn),
         .write_index(instr[4:3]),
         .op0_idx(instr[4:3]),
         .op1_idx(instr[2:1]),
@@ -39,6 +40,7 @@ module CPU9bits(
     RegFile Bank(
         .clk(clk),
         .reset(reset),
+        .enable(bankS[1]),
         .write_index(instr[2:1]),
         .op0_idx(instr[2:1]),
         .op1_idx(2'b00),//Doesn't matter