From f4c923f60cec4f8cfd1d8c2d57fc456d2c356a2f Mon Sep 17 00:00:00 2001 From: WilliamMiceli Date: Fri, 15 Feb 2019 16:19:42 -0500 Subject: [PATCH] Fixed ALU to use the inputs we're actually going to be giving it --- lab2CA.srcs/sources_1/new/ALU.v | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v index 95e2828..4a1b181 100644 --- a/lab2CA.srcs/sources_1/new/ALU.v +++ b/lab2CA.srcs/sources_1/new/ALU.v @@ -1,7 +1,9 @@ `timescale 1ns / 1ps module ALU( - input wire [8:0] instruction, + input wire [3:0] opcode, + input wire [8:0] operand0, + input wire [8:0] operand1, output wire [8:0] result ); @@ -18,7 +20,7 @@ module ALU( // MUX chooses which result to show based on the OPCODE mux_16_1 mux_result( - .switch(instruction[8:5]), + .switch(opcode), .A(A), .B(B), .C(C),