diff --git a/lab2CA.cache/wt/webtalk_pa.xml b/lab2CA.cache/wt/webtalk_pa.xml index ae8a1a9..04ee3a5 100644 --- a/lab2CA.cache/wt/webtalk_pa.xml +++ b/lab2CA.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -17,26 +17,49 @@ This means code written to parse this file will need to be revisited each subseq - - + + + + + + + + + - - - - + + + + + - + + + + + + + + + + + + + + + + - + - +
diff --git a/lab2CA.runs/.jobs/vrs_config_14.xml b/lab2CA.runs/.jobs/vrs_config_14.xml new file mode 100644 index 0000000..99236b3 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_14.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_15.xml b/lab2CA.runs/.jobs/vrs_config_15.xml new file mode 100644 index 0000000..99236b3 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_15.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/.jobs/vrs_config_16.xml b/lab2CA.runs/.jobs/vrs_config_16.xml new file mode 100644 index 0000000..99236b3 --- /dev/null +++ b/lab2CA.runs/.jobs/vrs_config_16.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab2CA.runs/synth_1/ALU.vds b/lab2CA.runs/synth_1/ALU.vds deleted file mode 100644 index 7152285..0000000 --- a/lab2CA.runs/synth_1/ALU.vds +++ /dev/null @@ -1,64 +0,0 @@ -#----------------------------------------------------------- -# Vivado v2018.3 (64-bit) -# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 -# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 13:03:34 2019 -# Process ID: 11092 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1 -# Command line: vivado.exe -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/ALU.vds -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou -#----------------------------------------------------------- -source ALU.tcl -notrace -Command: synth_design -top ALU -part xc7k160tifbg484-2L -Starting synth_design -Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' -INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' -INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 18316 ---------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 363.020 ; gain = 100.695 ---------------------------------------------------------------------------------- -INFO: [Synth 8-6157] synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3] -INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15] -INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] -INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (1#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] -INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (2#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15] -WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:14] -INFO: [Synth 8-6157] synthesizing module 'sub_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:480] -INFO: [Synth 8-6157] synthesizing module 'twos_compliment_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:499] -INFO: [Synth 8-6157] synthesizing module 'not_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316] -INFO: [Synth 8-6157] synthesizing module 'not_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:308] -INFO: [Synth 8-6155] done synthesizing module 'not_1bit' (3#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:308] -INFO: [Synth 8-6155] done synthesizing module 'not_9bit' (4#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:316] -WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:509] -INFO: [Synth 8-6155] done synthesizing module 'twos_compliment_9bit' (5#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:499] -WARNING: [Synth 8-350] instance 'add0' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:491] -INFO: [Synth 8-6155] done synthesizing module 'sub_9bit' (6#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:480] -INFO: [Synth 8-6157] synthesizing module 'or_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:367] -INFO: [Synth 8-6157] synthesizing module 'or_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:358] -INFO: [Synth 8-6155] done synthesizing module 'or_1bit' (7#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:358] -INFO: [Synth 8-6155] done synthesizing module 'or_9bit' (8#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:367] -INFO: [Synth 8-6157] synthesizing module 'nor_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:256] -INFO: [Synth 8-6157] synthesizing module 'nor_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:247] -INFO: [Synth 8-6155] done synthesizing module 'nor_1bit' (9#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:247] -INFO: [Synth 8-6155] done synthesizing module 'nor_9bit' (10#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:256] -WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:35] -INFO: [Synth 8-6157] synthesizing module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:105] -INFO: [Synth 8-6157] synthesizing module 'and_1bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:96] -INFO: [Synth 8-6155] done synthesizing module 'and_1bit' (11#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:96] -INFO: [Synth 8-6155] done synthesizing module 'and_9bit' (12#1) [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:105] -ERROR: [Synth 8-448] named port connection 'Cin' does not exist for instance 'and0' of module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:38] -ERROR: [Synth 8-448] named port connection 'Sum' does not exist for instance 'and0' of module 'and_9bit' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:39] -INFO: [Synth 8-6157] synthesizing module 'shift_logical_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:462] -ERROR: [Synth 8-6156] failed synthesizing module 'shift_logical_left' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v:462] -ERROR: [Synth 8-6156] failed synthesizing module 'ALU' [C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v:3] ---------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 419.512 ; gain = 157.188 ---------------------------------------------------------------------------------- -synthesize failed -INFO: [Common 17-83] Releasing license: Synthesis -28 Infos, 4 Warnings, 0 Critical Warnings and 5 Errors encountered. -synth_design failed -ERROR: [Common 17-69] Command failed: Vivado Synthesis failed -INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 13:03:44 2019... diff --git a/lab2CA.runs/synth_1/FetchUnit.dcp b/lab2CA.runs/synth_1/FetchUnit.dcp new file mode 100644 index 0000000..8a4f51f Binary files /dev/null and b/lab2CA.runs/synth_1/FetchUnit.dcp differ diff --git a/lab2CA.runs/synth_1/ALU.tcl b/lab2CA.runs/synth_1/FetchUnit.tcl similarity index 67% rename from lab2CA.runs/synth_1/ALU.tcl rename to lab2CA.runs/synth_1/FetchUnit.tcl index 7de6b1a..90d7f1b 100644 --- a/lab2CA.runs/synth_1/ALU.tcl +++ b/lab2CA.runs/synth_1/FetchUnit.tcl @@ -17,20 +17,23 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } +set_param synth.incrementalSynthesisCache C:/Users/ecelab/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-2460-DESKTOP-8QFGS52/incrSyn +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 create_project -in_memory -part xc7k160tifbg484-2L set_param project.singleFileAddWarning.threshold 0 set_param project.compositeFile.enableAutoGeneration 0 set_param synth.vivado.isSynthRun true -set_property webtalk.parent_dir {C:/Users/JoseIgnacio/CA Lab/lab2CA.cache/wt} [current_project] -set_property parent.project_path {C:/Users/JoseIgnacio/CA Lab/lab2CA.xpr} [current_project] +set_property webtalk.parent_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.cache/wt [current_project] +set_property parent.project_path C:/Users/ecelab/ECE3570-Lab/lab2CA.xpr [current_project] set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] -set_property ip_output_repo {c:/Users/JoseIgnacio/CA Lab/lab2CA.cache/ip} [current_project] +set_property ip_output_repo c:/Users/ecelab/ECE3570-Lab/lab2CA.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] read_verilog -library xil_defaultlib { - {C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/BasicModules.v} - {C:/Users/JoseIgnacio/CA Lab/lab2CA.srcs/sources_1/new/ALU.v} + C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v + C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v } # Mark all dcp files as not used in implementation to prevent them from being # stitched into the results of this synthesis run. Any black boxes in the @@ -43,12 +46,12 @@ foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { set_param ips.enableIPCacheLiteLoad 1 close [open __synthesis_is_running__ w] -synth_design -top ALU -part xc7k160tifbg484-2L +synth_design -top FetchUnit -part xc7k160tifbg484-2L # disable binary constraint mode for synth run checkpoints set_param constraints.enableBinaryConstraints false -write_checkpoint -force -noxdef ALU.dcp -create_report "synth_1_synth_report_utilization_0" "report_utilization -file ALU_utilization_synth.rpt -pb ALU_utilization_synth.pb" +write_checkpoint -force -noxdef FetchUnit.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb" file delete __synthesis_is_running__ close [open __synthesis_is_complete__ w] diff --git a/lab2CA.runs/synth_1/FetchUnit.vds b/lab2CA.runs/synth_1/FetchUnit.vds new file mode 100644 index 0000000..76d3558 --- /dev/null +++ b/lab2CA.runs/synth_1/FetchUnit.vds @@ -0,0 +1,260 @@ +#----------------------------------------------------------- +# Vivado v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 13:26:21 2019 +# Process ID: 8540 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 +# Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source FetchUnit.tcl -notrace +Command: synth_design -top FetchUnit -part xc7k160tifbg484-2L +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160ti' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160ti' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 11484 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 360.121 ; gain = 102.227 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'FetchUnit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] +INFO: [Synth 8-6157] synthesizing module 'register' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:419] +INFO: [Synth 8-6155] done synthesizing module 'register' (1#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:419] +INFO: [Synth 8-6157] synthesizing module 'add_9bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15] +INFO: [Synth 8-6157] synthesizing module 'add_1bit' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] +INFO: [Synth 8-6155] done synthesizing module 'add_1bit' (2#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:3] +INFO: [Synth 8-6155] done synthesizing module 'add_9bit' (3#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:15] +WARNING: [Synth 8-350] instance 'PCAdder' of module 'add_9bit' requires 5 connections, but only 4 given [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:18] +INFO: [Synth 8-6157] synthesizing module 'mux_2_1' [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:167] +INFO: [Synth 8-226] default block is never used [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:172] +INFO: [Synth 8-6155] done synthesizing module 'mux_2_1' (4#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/BasicModules.v:167] +INFO: [Synth 8-6155] done synthesizing module 'FetchUnit' (5#1) [C:/Users/ecelab/ECE3570-Lab/lab2CA.srcs/sources_1/new/FetchUnit.v:3] +WARNING: [Synth 8-3331] design FetchUnit has unconnected port write_index[1] +WARNING: [Synth 8-3331] design FetchUnit has unconnected port write_index[0] +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.043 ; gain = 158.148 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.043 ; gain = 158.148 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7k160tifbg484-2L +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.043 ; gain = 158.148 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7k160tifbg484-2L +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 416.043 ; gain = 158.148 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 18 ++---Registers : + 9 Bit Registers := 1 ++---Muxes : + 2 Input 9 Bit Muxes := 2 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module register +Detailed RTL Component Info : ++---Registers : + 9 Bit Registers := 1 ++---Muxes : + 2 Input 9 Bit Muxes := 1 +Module add_1bit +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 2 +Module mux_2_1 +Detailed RTL Component Info : ++---Muxes : + 2 Input 9 Bit Muxes := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 600 (col length:100) +BRAMs: 650 (col length: RAMB18 100 RAMB36 50) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3331] design FetchUnit has unconnected port write_index[1] +WARNING: [Synth 8-3331] design FetchUnit has unconnected port write_index[0] +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 579.223 ; gain = 321.328 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 579.223 ; gain = 321.328 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 579.223 ; gain = 321.328 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |BUFG | 1| +|2 |LUT1 | 1| +|3 |LUT2 | 1| +|4 |LUT3 | 2| +|5 |LUT4 | 5| +|6 |LUT5 | 5| +|7 |LUT6 | 6| +|8 |FDRE | 9| +|9 |IBUF | 12| +|10 |OBUF | 9| ++------+-----+------+ + +Report Instance Areas: ++------+---------+---------+------+ +| |Instance |Module |Cells | ++------+---------+---------+------+ +|1 |top | | 51| +|2 | PC |register | 29| ++------+---------+---------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +Synthesis Optimization Complete : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 579.223 ; gain = 321.328 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 677.328 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +18 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:22 . Memory (MB): peak = 677.328 ; gain = 419.434 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 677.328 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Sat Feb 16 13:26:46 2019... diff --git a/lab2CA.runs/synth_1/FetchUnit_utilization_synth.pb b/lab2CA.runs/synth_1/FetchUnit_utilization_synth.pb new file mode 100644 index 0000000..83594ed Binary files /dev/null and b/lab2CA.runs/synth_1/FetchUnit_utilization_synth.pb differ diff --git a/lab2CA.runs/synth_1/FetchUnit_utilization_synth.rpt b/lab2CA.runs/synth_1/FetchUnit_utilization_synth.rpt new file mode 100644 index 0000000..7135af6 --- /dev/null +++ b/lab2CA.runs/synth_1/FetchUnit_utilization_synth.rpt @@ -0,0 +1,182 @@ +Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 +| Date : Sat Feb 16 13:26:46 2019 +| Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) +| Command : report_utilization -file FetchUnit_utilization_synth.rpt -pb FetchUnit_utilization_synth.pb +| Design : FetchUnit +| Device : 7k160tifbg484-2L +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 15 | 0 | 101400 | 0.01 | +| LUT as Logic | 15 | 0 | 101400 | 0.01 | +| LUT as Memory | 0 | 0 | 35000 | 0.00 | +| Slice Registers | 9 | 0 | 202800 | <0.01 | +| Register as Flip Flop | 9 | 0 | 202800 | <0.01 | +| Register as Latch | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 25350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 9 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 325 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 325 | 0.00 | +| RAMB18 | 0 | 0 | 650 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 600 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 21 | 0 | 285 | 7.37 | +| Bonded IPADs | 0 | 0 | 14 | 0.00 | +| Bonded OPADs | 0 | 0 | 8 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 275 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 1 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 4 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 2 | 0.00 | +| ILOGIC | 0 | 0 | 285 | 0.00 | +| OLOGIC | 0 | 0 | 285 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 1 | 0 | 32 | 3.13 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 120 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| IBUF | 12 | IO | +| OBUF | 9 | IO | +| FDRE | 9 | Flop & Latch | +| LUT6 | 6 | LUT | +| LUT5 | 5 | LUT | +| LUT4 | 5 | LUT | +| LUT3 | 2 | LUT | +| LUT2 | 1 | LUT | +| LUT1 | 1 | LUT | +| BUFG | 1 | Clock | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/lab2CA.runs/synth_1/gen_run.xml b/lab2CA.runs/synth_1/gen_run.xml index dd771bf..7b1581b 100644 --- a/lab2CA.runs/synth_1/gen_run.xml +++ b/lab2CA.runs/synth_1/gen_run.xml @@ -1,14 +1,14 @@ - - - - - - - - - - + + + + + + + + + + @@ -18,7 +18,7 @@ - + @@ -33,7 +33,7 @@ - + @@ -43,7 +43,7 @@ diff --git a/lab2CA.runs/synth_1/htr.txt b/lab2CA.runs/synth_1/htr.txt index 1c28ba9..f27554f 100644 --- a/lab2CA.runs/synth_1/htr.txt +++ b/lab2CA.runs/synth_1/htr.txt @@ -6,4 +6,4 @@ REM to be invoked for Vivado to track run status. REM Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. REM -vivado -log ALU.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl +vivado -log FetchUnit.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl diff --git a/lab2CA.runs/synth_1/vivado.jou b/lab2CA.runs/synth_1/vivado.jou index 38475ab..432a836 100644 --- a/lab2CA.runs/synth_1/vivado.jou +++ b/lab2CA.runs/synth_1/vivado.jou @@ -2,11 +2,11 @@ # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 -# Start of session at: Sat Feb 16 13:03:34 2019 -# Process ID: 11092 -# Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1 -# Command line: vivado.exe -log ALU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ALU.tcl -# Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1/ALU.vds -# Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/synth_1\vivado.jou +# Start of session at: Sat Feb 16 13:26:21 2019 +# Process ID: 8540 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1 +# Command line: vivado.exe -log FetchUnit.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source FetchUnit.tcl +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1/FetchUnit.vds +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.runs/synth_1\vivado.jou #----------------------------------------------------------- -source ALU.tcl -notrace +source FetchUnit.tcl -notrace diff --git a/lab2CA.runs/synth_1/vivado.pb b/lab2CA.runs/synth_1/vivado.pb index c77a056..314ae08 100644 Binary files a/lab2CA.runs/synth_1/vivado.pb and b/lab2CA.runs/synth_1/vivado.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/ALU.tcl b/lab2CA.sim/sim_1/behav/xsim/ALU.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/ALU.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/ALU_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/ALU_vlog.prj new file mode 100644 index 0000000..1efb11b --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/ALU_vlog.prj @@ -0,0 +1,10 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ +"../../../../lab2CA.srcs/sources_1/new/ALU.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/add1bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/add1bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/add1bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/add1bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/add1bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/add1bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/add9bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/add9bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/add9bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/add9bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/add9bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/add9bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/and1bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/and1bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/and1bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/and1bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/and1bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/and1bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/and9bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/and9bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/and9bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/and9bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/and9bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/and9bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/glbl.v b/lab2CA.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..be64233 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/lab2CA.sim/sim_1/behav/xsim/mux_2_1_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/mux_2_1_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/mux_2_1_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/mux_2_1_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/mux_2_1_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/mux_2_1_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/mux_4_1_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/mux_4_1_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/mux_4_1_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/mux_4_1_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/mux_4_1_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/mux_4_1_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/mux_8_1_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/mux_8_1_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/mux_8_1_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/mux_8_1_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/mux_8_1_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/mux_8_1_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/nor_1bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/nor_1bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/nor_1bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/nor_1bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/nor_1bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/nor_1bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/nor_9bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/nor_9bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/nor_9bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/nor_9bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/nor_9bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/nor_9bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/not_1bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/not_1bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/not_1bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/not_1bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/not_1bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/not_1bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/not_9bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/not_9bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/not_9bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/not_9bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/not_9bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/not_9bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/or_1bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/or_1bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/or_1bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/or_1bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/or_1bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/or_1bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/or_9bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/or_9bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/or_9bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/or_9bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/or_9bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/or_9bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/register_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/register_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/register_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/register_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/register_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/register_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/shift_logical_left_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/shift_logical_left_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/shift_logical_left_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/shift_logical_left_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/shift_logical_left_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/shift_logical_left_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/shift_logical_right_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/shift_logical_right_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/shift_logical_right_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/shift_logical_right_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/shift_logical_right_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/shift_logical_right_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/sub_9bit_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/sub_9bit_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/sub_9bit_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/sub_9bit_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/sub_9bit_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/sub_9bit_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/twos_compliment_tb.tcl b/lab2CA.sim/sim_1/behav/xsim/twos_compliment_tb.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/twos_compliment_tb.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/lab2CA.sim/sim_1/behav/xsim/twos_compliment_tb_vlog.prj b/lab2CA.sim/sim_1/behav/xsim/twos_compliment_tb_vlog.prj new file mode 100644 index 0000000..c097ced --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/twos_compliment_tb_vlog.prj @@ -0,0 +1,9 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib \ +"../../../../lab2CA.srcs/sources_1/new/BasicModules.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou new file mode 100644 index 0000000..c42d9ad --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 16:27:58 2019 +# Process ID: 12116 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_1120.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_1120.backup.jou new file mode 100644 index 0000000..5d7c550 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_1120.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 16:08:33 2019 +# Process ID: 1120 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_11256.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_11256.backup.jou new file mode 100644 index 0000000..0644290 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_11256.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 16:26:27 2019 +# Process ID: 11256 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_1276.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_1276.backup.jou new file mode 100644 index 0000000..51fb553 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_1276.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 16:09:25 2019 +# Process ID: 1276 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_13392.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_13392.backup.jou new file mode 100644 index 0000000..0805a63 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_13392.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 16:22:35 2019 +# Process ID: 13392 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/webtalk_6756.backup.jou b/lab2CA.sim/sim_1/behav/xsim/webtalk_6756.backup.jou new file mode 100644 index 0000000..970f9c6 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/webtalk_6756.backup.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Webtalk v2018.3 (64-bit) +# SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 +# IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 +# Start of session at: Sat Feb 16 16:24:44 2019 +# Process ID: 6756 +# Current directory: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim +# Command line: wbtcv.exe -mode batch -source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace +# Log file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/webtalk.log +# Journal file: C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim\webtalk.jou +#----------------------------------------------------------- +source C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/xsim_webtalk.tcl -notrace diff --git a/lab2CA.sim/sim_1/behav/xsim/xelab.pb b/lab2CA.sim/sim_1/behav/xsim/xelab.pb new file mode 100644 index 0000000..20a959c Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xelab.pb differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/Compile_Options.txt new file mode 100644 index 0000000..ecdbe45 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "ALU_behav" "xil_defaultlib.ALU" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/obj/xsim_1.c new file mode 100644 index 0000000..352039c --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/obj/xsim_1.c @@ -0,0 +1,115 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_178(char*, char *); +extern void execute_82(char*, char *); +extern void execute_83(char*, char *); +extern void execute_127(char*, char *); +extern void execute_100(char*, char *); +extern void execute_148(char*, char *); +extern void execute_157(char*, char *); +extern void execute_166(char*, char *); +extern void execute_175(char*, char *); +extern void execute_176(char*, char *); +extern void execute_77(char*, char *); +extern void execute_79(char*, char *); +extern void execute_80(char*, char *); +extern void execute_81(char*, char *); +extern void execute_179(char*, char *); +extern void execute_180(char*, char *); +extern void execute_181(char*, char *); +extern void execute_182(char*, char *); +extern void execute_183(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[21] = {(funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_178, (funcp)execute_82, (funcp)execute_83, (funcp)execute_127, (funcp)execute_100, (funcp)execute_148, (funcp)execute_157, (funcp)execute_166, (funcp)execute_175, (funcp)execute_176, (funcp)execute_77, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_179, (funcp)execute_180, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 21; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/ALU_behav/xsim.reloc", (void **)funcTab, 21); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/ALU_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/ALU_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/ALU_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/ALU_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/ALU_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..073bf09 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/xsim.mem new file mode 100644 index 0000000..2c196e5 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/ALU_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..693fcb3 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "add1bit_tb_behav" "xil_defaultlib.add1bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..2bd2442 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_8(char*, char *); +extern void execute_9(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_3, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_8, (funcp)execute_9, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/add1bit_tb_behav/xsim.reloc", (void **)funcTab, 15); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/add1bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/add1bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/add1bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/add1bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/add1bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..b4ca08d --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/xsim.mem new file mode 100644 index 0000000..8f3c299 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add1bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..17cfe5c --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "add9bit_tb_behav" "xil_defaultlib.add9bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..71b4ad1 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_12(char*, char *); +extern void execute_35(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_38(char*, char *); +extern void execute_39(char*, char *); +extern void execute_40(char*, char *); +extern void execute_41(char*, char *); +extern void execute_42(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_12, (funcp)execute_35, (funcp)execute_36, (funcp)execute_37, (funcp)execute_17, (funcp)execute_18, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_38, (funcp)execute_39, (funcp)execute_40, (funcp)execute_41, (funcp)execute_42, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/add9bit_tb_behav/xsim.reloc", (void **)funcTab, 15); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/add9bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/add9bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/add9bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/add9bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/add9bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..18d283b --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/xsim.mem new file mode 100644 index 0000000..5434136 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/add9bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..f4361a8 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "and1bit_tb_behav" "xil_defaultlib.and1bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..9d3f44f --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,107 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_8(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[13] = {(funcp)execute_3, (funcp)execute_9, (funcp)execute_10, (funcp)execute_8, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 13; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/and1bit_tb_behav/xsim.reloc", (void **)funcTab, 13); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/and1bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/and1bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/and1bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/and1bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/and1bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..2f389c8 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/xsim.mem new file mode 100644 index 0000000..d42d469 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and1bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..4167aad --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "and9bit_tb_behav" "xil_defaultlib.and9bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..95c0ca6 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,107 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_12(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_17(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[13] = {(funcp)execute_12, (funcp)execute_26, (funcp)execute_27, (funcp)execute_17, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 13; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/and9bit_tb_behav/xsim.reloc", (void **)funcTab, 13); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/and9bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/and9bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/and9bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/and9bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/and9bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..22c4221 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/xsim.mem new file mode 100644 index 0000000..6aa1ebb Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/and9bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..fd1a31a --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "mux_2_1_tb_behav" "xil_defaultlib.mux_2_1_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..b44e657 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/obj/xsim_1.c @@ -0,0 +1,109 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[15] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 15; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/mux_2_1_tb_behav/xsim.reloc", (void **)funcTab, 15); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/mux_2_1_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/mux_2_1_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/mux_2_1_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/mux_2_1_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/mux_2_1_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..7eac5e2 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..7a70894 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Feb 16 15:07:50 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "6" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "30 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.19_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6076_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1598164678 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/xsim.mem new file mode 100644 index 0000000..4f75283 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_2_1_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..4f0137f --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "mux_4_1_tb_behav" "xil_defaultlib.mux_4_1_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..777adcb --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/obj/xsim_1.c @@ -0,0 +1,111 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_19(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[17] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 17; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/mux_4_1_tb_behav/xsim.reloc", (void **)funcTab, 17); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/mux_4_1_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/mux_4_1_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/mux_4_1_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/mux_4_1_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/mux_4_1_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..11d6577 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..92a12f3 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Feb 16 15:07:46 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "20 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.23_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6108_KB" -context "xsim\\usage" +webtalk_transmit -clientid 2046978020 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/xsim.mem new file mode 100644 index 0000000..d91a596 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_4_1_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..35a2bcd --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "mux_8_1_tb_behav" "xil_defaultlib.mux_8_1_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..3fc21e2 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/obj/xsim_1.c @@ -0,0 +1,115 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_19(char*, char *); +extern void execute_20(char*, char *); +extern void execute_21(char*, char *); +extern void execute_22(char*, char *); +extern void execute_23(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[21] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 21; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/mux_8_1_tb_behav/xsim.reloc", (void **)funcTab, 21); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/mux_8_1_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/mux_8_1_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/mux_8_1_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/mux_8_1_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/mux_8_1_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..6d69751 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..f246fe5 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Feb 16 15:07:40 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "40 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.09_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6100_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1575132653 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/xsim.mem new file mode 100644 index 0000000..427de31 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/mux_8_1_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..d39918e --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "nor_1bit_tb_behav" "xil_defaultlib.nor_1bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..97e2141 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,107 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_8(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[13] = {(funcp)execute_3, (funcp)execute_9, (funcp)execute_10, (funcp)execute_8, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 13; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/nor_1bit_tb_behav/xsim.reloc", (void **)funcTab, 13); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/nor_1bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/nor_1bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/nor_1bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/nor_1bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/nor_1bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..0f0f9af --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..e66ff1f --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Feb 16 15:06:54 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "4" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "20 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.06_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6056_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1409759586 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/xsim.mem new file mode 100644 index 0000000..f8a0ae7 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_1bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..cff7a07 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "nor_9bit_tb_behav" "xil_defaultlib.nor_9bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..9dfa001 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,107 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_12(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_17(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[13] = {(funcp)execute_12, (funcp)execute_26, (funcp)execute_27, (funcp)execute_17, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 13; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/nor_9bit_tb_behav/xsim.reloc", (void **)funcTab, 13); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/nor_9bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/nor_9bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/nor_9bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/nor_9bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/nor_9bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..a0e8de4 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/xsim.mem new file mode 100644 index 0000000..670c599 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/nor_9bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..deb17ac --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "not_1bit_tb_behav" "xil_defaultlib.not_1bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..65f3535 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,106 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_9(char*, char *); +extern void execute_8(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[12] = {(funcp)execute_3, (funcp)execute_9, (funcp)execute_8, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 12; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/not_1bit_tb_behav/xsim.reloc", (void **)funcTab, 12); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/not_1bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/not_1bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/not_1bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/not_1bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/not_1bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..aa937b6 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/xsim.mem new file mode 100644 index 0000000..9ae0930 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_1bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..458afe5 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "not_9bit_tb_behav" "xil_defaultlib.not_9bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..f3ad8dc --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,106 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_12(char*, char *); +extern void execute_26(char*, char *); +extern void execute_17(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_27(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[12] = {(funcp)execute_12, (funcp)execute_26, (funcp)execute_17, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 12; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/not_9bit_tb_behav/xsim.reloc", (void **)funcTab, 12); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/not_9bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/not_9bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/not_9bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/not_9bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/not_9bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..87748d6 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..aa20668 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Feb 16 15:19:42 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "8" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "35 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6104_KB" -context "xsim\\usage" +webtalk_transmit -clientid 61314925 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/xsim.mem new file mode 100644 index 0000000..3363def Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/not_9bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..1ba4f8a --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "or_1bit_tb_behav" "xil_defaultlib.or_1bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..3afafb1 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,107 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_8(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[13] = {(funcp)execute_3, (funcp)execute_9, (funcp)execute_10, (funcp)execute_8, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 13; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/or_1bit_tb_behav/xsim.reloc", (void **)funcTab, 13); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/or_1bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/or_1bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/or_1bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/or_1bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/or_1bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..6733f19 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/xsim.mem new file mode 100644 index 0000000..03f6796 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_1bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..dcf7bd0 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "or_9bit_tb_behav" "xil_defaultlib.or_9bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..a506630 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,107 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_12(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_17(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_28(char*, char *); +extern void execute_29(char*, char *); +extern void execute_30(char*, char *); +extern void execute_31(char*, char *); +extern void execute_32(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[13] = {(funcp)execute_12, (funcp)execute_26, (funcp)execute_27, (funcp)execute_17, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)execute_31, (funcp)execute_32, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 13; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/or_9bit_tb_behav/xsim.reloc", (void **)funcTab, 13); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/or_9bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/or_9bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/or_9bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/or_9bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/or_9bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..0e2b478 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/xsim.mem new file mode 100644 index 0000000..5524fd4 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/or_9bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..964ef6d --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "register_tb_behav" "xil_defaultlib.register_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..6998075 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/obj/xsim_1.c @@ -0,0 +1,110 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_4(char*, char *); +extern void execute_9(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_3(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_8(char*, char *); +extern void execute_14(char*, char *); +extern void execute_15(char*, char *); +extern void execute_16(char*, char *); +extern void execute_17(char*, char *); +extern void execute_18(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[16] = {(funcp)execute_4, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 16; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/register_tb_behav/xsim.reloc", (void **)funcTab, 16); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/register_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/register_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/register_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/register_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/register_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..91a86c5 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/xsim_webtalk.tcl b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/xsim_webtalk.tcl new file mode 100644 index 0000000..31f24a1 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/xsim_webtalk.tcl @@ -0,0 +1,32 @@ +webtalk_init -webtalk_dir C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/ +webtalk_register_client -client project +webtalk_add_data -client project -key date_generated -value "Sat Feb 16 16:02:04 2019" -context "software_version_and_target_device" +webtalk_add_data -client project -key product_version -value "XSIM v2018.3 (64-bit)" -context "software_version_and_target_device" +webtalk_add_data -client project -key build_version -value "2405991" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" +webtalk_add_data -client project -key registration_id -value "174150793_174150794_210688225_140" -context "software_version_and_target_device" +webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" +webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" +webtalk_add_data -client project -key random_id -value "4e917e26-7591-4435-9135-15bd446b0238" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_id -value "0a5803efda44405bb28bbf43ba22e808" -context "software_version_and_target_device" +webtalk_add_data -client project -key project_iteration -value "10" -context "software_version_and_target_device" +webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" +webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" +webtalk_add_data -client project -key cpu_name -value "Intel(R) Xeon(R) CPU E5-1620 v3 @ 3.50GHz" -context "user_environment" +webtalk_add_data -client project -key cpu_speed -value "3492 MHz" -context "user_environment" +webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" +webtalk_add_data -client project -key system_ram -value "34.000 GB" -context "user_environment" +webtalk_register_client -client xsim +webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" +webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" +webtalk_add_data -client xsim -key runtime -value "55 ns" -context "xsim\\usage" +webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Time -value "0.05_sec" -context "xsim\\usage" +webtalk_add_data -client xsim -key Simulation_Memory -value "6088_KB" -context "xsim\\usage" +webtalk_transmit -clientid 1216100017 -regid "174150793_174150794_210688225_140" -xml C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm C:/Users/ecelab/ECE3570-Lab/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" +webtalk_terminate diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/xsim.mem new file mode 100644 index 0000000..8d9f00e Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/register_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..04c67f6 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "shift_logical_left_tb_behav" "xil_defaultlib.shift_logical_left_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..9500c99 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/obj/xsim_1.c @@ -0,0 +1,106 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_9(char*, char *); +extern void execute_8(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[12] = {(funcp)execute_3, (funcp)execute_9, (funcp)execute_8, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 12; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/shift_logical_left_tb_behav/xsim.reloc", (void **)funcTab, 12); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/shift_logical_left_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/shift_logical_left_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/shift_logical_left_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/shift_logical_left_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/shift_logical_left_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..b5cf73b --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/xsim.mem new file mode 100644 index 0000000..1f1bdde Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_left_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..1470e54 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "shift_logical_right_tb_behav" "xil_defaultlib.shift_logical_right_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..4be07df --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/obj/xsim_1.c @@ -0,0 +1,106 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_3(char*, char *); +extern void execute_9(char*, char *); +extern void execute_8(char*, char *); +extern void execute_5(char*, char *); +extern void execute_6(char*, char *); +extern void execute_7(char*, char *); +extern void execute_10(char*, char *); +extern void execute_11(char*, char *); +extern void execute_12(char*, char *); +extern void execute_13(char*, char *); +extern void execute_14(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[12] = {(funcp)execute_3, (funcp)execute_9, (funcp)execute_8, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 12; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/shift_logical_right_tb_behav/xsim.reloc", (void **)funcTab, 12); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/shift_logical_right_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/shift_logical_right_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/shift_logical_right_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/shift_logical_right_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/shift_logical_right_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..182f0c3 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/xsim.mem new file mode 100644 index 0000000..d64e8a0 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/shift_logical_right_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..426d51a --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "sub_9bit_tb_behav" "xil_defaultlib.sub_9bit_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..66c0d66 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/obj/xsim_1.c @@ -0,0 +1,111 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_34(char*, char *); +extern void execute_87(char*, char *); +extern void execute_88(char*, char *); +extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_66(char*, char *); +extern void execute_39(char*, char *); +extern void execute_48(char*, char *); +extern void execute_49(char*, char *); +extern void execute_36(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_89(char*, char *); +extern void execute_90(char*, char *); +extern void execute_91(char*, char *); +extern void execute_92(char*, char *); +extern void execute_93(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[17] = {(funcp)execute_34, (funcp)execute_87, (funcp)execute_88, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_66, (funcp)execute_39, (funcp)execute_48, (funcp)execute_49, (funcp)execute_36, (funcp)execute_37, (funcp)execute_38, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_93, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 17; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/sub_9bit_tb_behav/xsim.reloc", (void **)funcTab, 17); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/sub_9bit_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/sub_9bit_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/sub_9bit_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/sub_9bit_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/sub_9bit_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..b98ad53 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/xsim.mem new file mode 100644 index 0000000..a4e8e00 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/sub_9bit_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/Compile_Options.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/Compile_Options.txt new file mode 100644 index 0000000..68b0f74 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/Compile_Options.txt @@ -0,0 +1 @@ +-wto "0a5803efda44405bb28bbf43ba22e808" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "twos_compliment_tb_behav" "xil_defaultlib.twos_compliment_tb" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/TempBreakPointFile.txt b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/obj/xsim_1.c b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/obj/xsim_1.c new file mode 100644 index 0000000..694a47e --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/obj/xsim_1.c @@ -0,0 +1,110 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/**********************************************************************/ + + +#include "iki.h" +#include +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +typedef void (*funcp)(char *, char *); +extern int main(int, char**); +extern void execute_23(char*, char *); +extern void execute_57(char*, char *); +extern void execute_55(char*, char *); +extern void vlog_const_rhs_process_execute_0_fast_no_reg_no_agg(char*, char*, char*); +extern void execute_28(char*, char *); +extern void execute_37(char*, char *); +extern void execute_38(char*, char *); +extern void execute_25(char*, char *); +extern void execute_26(char*, char *); +extern void execute_27(char*, char *); +extern void execute_58(char*, char *); +extern void execute_59(char*, char *); +extern void execute_60(char*, char *); +extern void execute_61(char*, char *); +extern void execute_62(char*, char *); +extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); +funcp funcTab[16] = {(funcp)execute_23, (funcp)execute_57, (funcp)execute_55, (funcp)vlog_const_rhs_process_execute_0_fast_no_reg_no_agg, (funcp)execute_28, (funcp)execute_37, (funcp)execute_38, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_58, (funcp)execute_59, (funcp)execute_60, (funcp)execute_61, (funcp)execute_62, (funcp)vlog_transfunc_eventcallback}; +const int NumRelocateId= 16; + +void relocate(char *dp) +{ + iki_relocate(dp, "xsim.dir/twos_compliment_tb_behav/xsim.reloc", (void **)funcTab, 16); + + /*Populate the transaction function pointer field in the whole net structure */ +} + +void sensitize(char *dp) +{ + iki_sensitize(dp, "xsim.dir/twos_compliment_tb_behav/xsim.reloc"); +} + +void simulate(char *dp) +{ + iki_schedule_processes_at_time_zero(dp, "xsim.dir/twos_compliment_tb_behav/xsim.reloc"); + // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net + iki_execute_processes(); + + // Schedule resolution functions for the multiply driven Verilog nets that have strength + // Schedule transaction functions for the singly driven Verilog nets that have strength + +} +#include "iki_bridge.h" +void relocate(char *); + +void sensitize(char *); + +void simulate(char *); + +extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); +extern void implicit_HDL_SCinstatiate(); + +extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; +extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; + +int main(int argc, char **argv) +{ + iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; + iki_set_sv_type_file_path_name("xsim.dir/twos_compliment_tb_behav/xsim.svtype"); + iki_set_crvs_dump_file_path_name("xsim.dir/twos_compliment_tb_behav/xsim.crvsdump"); + void* design_handle = iki_create_design("xsim.dir/twos_compliment_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); + iki_set_rc_trial_count(100); + (void) design_handle; + return iki_simulate_design(); +} diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/usage_statistics_ext_xsim.xml b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/usage_statistics_ext_xsim.xml new file mode 100644 index 0000000..579b5e0 --- /dev/null +++ b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/webtalk/usage_statistics_ext_xsim.xml @@ -0,0 +1,44 @@ + + +
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+ diff --git a/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/xsim.mem b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/xsim.mem new file mode 100644 index 0000000..c12a7fc Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xsim.dir/twos_compliment_tb_behav/xsim.mem differ diff --git a/lab2CA.sim/sim_1/behav/xsim/xvlog.pb b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb new file mode 100644 index 0000000..0cba936 Binary files /dev/null and b/lab2CA.sim/sim_1/behav/xsim/xvlog.pb differ diff --git a/lab2CA.srcs/sources_1/new/ALU.v b/lab2CA.srcs/sources_1/new/ALU.v index 9d5deb4..c44f1c6 100644 --- a/lab2CA.srcs/sources_1/new/ALU.v +++ b/lab2CA.srcs/sources_1/new/ALU.v @@ -35,8 +35,7 @@ module ALU( and_9bit and0( .A(operand0), .B(operand1), - .Cin(1'b0), - .Sum(result_E)); + .C(result_E)); // F (101) - Shift Logical Left shift_logical_left sll( .A(operand0), diff --git a/lab2CA.srcs/sources_1/new/BasicModules.v b/lab2CA.srcs/sources_1/new/BasicModules.v index 001f115..fcbdbd9 100644 --- a/lab2CA.srcs/sources_1/new/BasicModules.v +++ b/lab2CA.srcs/sources_1/new/BasicModules.v @@ -12,6 +12,44 @@ module add_1bit( endmodule +//testbench +//module add1bit_tb(); +//reg v; +//reg w; +//reg x; +//wire y; +//wire z; + +//add_1bit add0( +// .A(v), +// .B(w), +// .Cin(x), +// .S(y), +// .Cout(z)); + +// initial begin +// v = 0; +// w = 0; +// x = 0; +// #5 +// v = 0; +// w = 1; +// x = 0; +// #5 +// v = 0; +// w = 0; +// x = 1; +// #5 +// v = 1; +// w = 1; +// x = 0; +// #5 +// v = 1; +// w = 1; +// x = 1; +// end +//endmodule + module add_9bit( input wire [8:0] A, input wire [8:0] B, @@ -93,6 +131,45 @@ module add_9bit( endmodule +//testbench +//module add9bit_tb(); +//reg [8:0] a; +//reg [8:0] b; +//reg cin; +//wire [8:0] s; +//wire cout; + +//add_9bit add0( +// .A(a), +// .B(b), +// .Cin(cin), +// .Sum(s), +// .Cout(cout)); + + +// initial begin +// a = 9'b000000000; +// b = 9'b000000000; +// cin = 0; +// #5 +// a = 9'b000000001; +// b = 9'b000000000; +// cin = 0; +// #5 +// a = 9'b000000000; +// b = 9'b000000001; +// cin = 1; +// #5 +// a = 9'b000000001; +// b = 9'b000000001; +// cin = 0; +// #5 +// a = 9'b000001000; +// b = 9'b000000001; +// cin = 1; +// end +//endmodule + module and_1bit( input wire A, input wire B, @@ -102,6 +179,34 @@ module and_1bit( endmodule +//testbench +//module and1bit_tb(); +//reg a; +//reg b; +//wire c; + +//and_1bit and0( +//.A(a), +//.B(b), +//.C(c)); + +// initial begin +// a = 0; +// b = 0; +// #5 +// a = 0; +// b = 1; +// #5 +// a = 1; +// b = 0; +// #5 +// a = 1; +// b = 1; +// #5 $finish; + +// end +//endmodule + module and_9bit( input wire [8:0] A, input wire [8:0] B, @@ -154,6 +259,40 @@ module and_9bit( endmodule +//testbench +//module and9bit_tb(); +//reg [8:0] a; +//reg [8:0] b; +//wire [8:0] c; + +//and_9bit and0( +//.A(a), +//.B(b), +//.C(c)); + +// initial begin +// a = 9'b000000000; +// b = 9'b000000000; +// #5 +// a = 9'b000000000; +// b = 9'b000000001; +// #5 +// a = 9'b000000001; +// b = 9'b000000000; +// #5 +// a = 9'b000000001; +// b = 9'b000000001; +// #5 +// a = 9'b000100001; +// b = 9'b000000001; +// #5 +// a = 9'b000100001; +// b = 9'b000100001; +// #5 $finish; + +// end +//endmodule + module gen_clock(); reg clk; initial begin @@ -164,6 +303,12 @@ module gen_clock(); end endmodule +// testbench +//module gen_clock_tb(); + +//reg clk; +// gen + module mux_2_1(input wire switch, input wire [8:0] A,B, output reg [8:0] out); @@ -178,6 +323,48 @@ module mux_2_1(input wire switch, endmodule +//testbench +//module mux_2_1_tb(); +//reg s; +//reg [8:0] a; +//reg [8:0] b; +//wire [8:0] c; + +//mux_2_1 mux0( +//.switch(s), +//.A(a), +//.B(b), +//.out(c)); + +// initial begin +// s = 0; +// a = 9'b000000101; +// b = 9'b000000000; +// #5 +// s = 1; +// a = 9'b000000001; +// b = 9'b000100001; +// #5 +// s = 0; +// a = 9'b000000000; +// b = 9'b000000001; +// #5 +// s = 1; +// a = 9'b000000001; +// b = 9'b000000001; +// #5 +// s = 0; +// a = 9'b000010001; +// b = 9'b000000001; +// #5 +// s = 1; +// a = 9'b000010001; +// b = 9'b000010111; +// #5 $finish; + +// end +//endmodule + module mux_4_1(input wire [1:0] switch, input wire [8:0] A,B,C,D, output reg [8:0] out); @@ -194,6 +381,52 @@ module mux_4_1(input wire [1:0] switch, endmodule +//testbench +//module mux_4_1_tb(); +//reg [1:0] s; +//reg [8:0] a; +//reg [8:0] b; +//reg [8:0] c; +//reg [8:0] d; +//wire [8:0] e; + +//mux_4_1 mux1( +//.switch(s), +//.A(a), +//.B(b), +//.C(c), +//.D(d), +//.out(e)); + +// initial begin +// s = 2'b00; +// a = 9'b000000101; +// b = 9'b000111100; +// c = 9'b001001001; +// d = 9'b100000000; +// #5 +// s = 2'b01; +// a = 9'b000000101; +// b = 9'b000111100; +// c = 9'b001001001; +// d = 9'b100000000; +// #5 +// s = 2'b10; +// a = 9'b000000101; +// b = 9'b000111100; +// c = 9'b001001001; +// d = 9'b100000000; +// #5 +// s = 2'b11; +// a = 9'b000000101; +// b = 9'b000111100; +// c = 9'b001001001; +// d = 9'b100000000; +// #5 $finish; + +// end +//endmodule + module mux_8_1( input wire [2:0] switch, input wire [8:0] A,B,C,D,E,F,G,H, @@ -215,44 +448,127 @@ module mux_8_1( endmodule -module mux_16_1( - input wire [3:0] switch, - input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P, - output reg [8:0] out); - - always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin - case (switch) - 4'b0000 : out = A; - 4'b0001 : out = B; - 4'b0010 : out = C; - 4'b0011 : out = D; - 4'b0100 : out = E; - 4'b0101 : out = F; - 4'b0110 : out = G; - 4'b0111 : out = H; - 4'b1000 : out = I; - 4'b1001 : out = J; - 4'b1010 : out = K; - 4'b1011 : out = L; - 4'b1100 : out = M; - 4'b1101 : out = N; - 4'b1110 : out = O; - 4'b1111 : out = P; - default : out = 9'bxxxxxxxxx; - endcase - end +//testbench +//module mux_8_1_tb(); +//reg [2:0] s; +//reg [8:0] a; +//reg [8:0] b; +//reg [8:0] c; +//reg [8:0] d; +//reg [8:0] e; +//reg [8:0] f; +//reg [8:0] g; +//reg [8:0] h; +//wire [8:0] out; -endmodule +//mux_8_1 mux1( +//.switch(s), +//.A(a), +//.B(b), +//.C(c), +//.D(d), +//.E(e), +//.F(f), +//.G(g), +//.H(h), +//.out(out)); + +// initial begin +// s = 3'b000; +// a = 9'b000000101; +// b = 9'b000111100; +// c = 9'b001001001; +// d = 9'b100110000; +// e = 9'b010000101; +// f = 9'b010111100; +// g = 9'b011001001; +// h = 9'b111000000; +// #5 +// s = 3'b001; +// #5 +// s = 3'b010; +// #5 +// s = 3'b011; +// #5 +// s = 3'b100; +// #5 +// s = 3'b101; +// #5 +// s = 3'b110; +// #5 +// s = 3'b111; +// #5 $finish; + +// end +//endmodule + +//module mux_16_1( +// input wire [3:0] switch, +// input wire [8:0] A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P, +// output reg [8:0] out); + +// always @(A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P,switch) begin +// case (switch) +// 4'b0000 : out = A; +// 4'b0001 : out = B; +// 4'b0010 : out = C; +// 4'b0011 : out = D; +// 4'b0100 : out = E; +// 4'b0101 : out = F; +// 4'b0110 : out = G; +// 4'b0111 : out = H; +// 4'b1000 : out = I; +// 4'b1001 : out = J; +// 4'b1010 : out = K; +// 4'b1011 : out = L; +// 4'b1100 : out = M; +// 4'b1101 : out = N; +// 4'b1110 : out = O; +// 4'b1111 : out = P; +// default : out = 9'bxxxxxxxxx; +// endcase +// end + +//endmodule module nor_1bit( input wire A, input wire B, output wire C); - assign C = A |~ B; + //assign C = A |~ B; + assign C = ~(A | B); endmodule +//testbench +//module nor_1bit_tb(); +//reg a; +//reg b; +//wire c; + +//nor_1bit nor0( +//.A(a), +//.B(b), +//.C(c)); + +// initial begin +// a = 0; +// b = 0; +// #5 +// a = 0; +// b = 1; +// #5 +// a = 1; +// b = 0; +// #5 +// a = 1; +// b = 1; +// #5 $finish; + +// end +//endmodule + module nor_9bit( input wire [8:0] A, input wire [8:0] B, @@ -305,6 +621,41 @@ module nor_9bit( endmodule +//testbench +//module nor_9bit_tb(); +//reg [8:0] a; +//reg [8:0] b; +//wire [8:0] c; + +//nor_9bit nor0( +//.A(a), +//.B(b), +//.C(c)); + +// initial begin +// a = 9'b000000000; +// b = 9'b000000000; +// #5 +// a = 9'b000000000; +// b = 9'b000000001; +// #5 +// a = 9'b000000001; +// b = 9'b000000000; +// #5 +// a = 9'b000000001; +// b = 9'b000000001; +// #5 +// a = 9'b000100001; +// b = 9'b000000001; +// #5 +// a = 9'b000100001; +// b = 9'b000100001; +// #5 $finish; + +// end +//endmodule + + module not_1bit( input wire A, output wire B); @@ -313,6 +664,24 @@ module not_1bit( endmodule +//testbench +//module not_1bit_tb(); +//reg a; +//wire b; + +//not_1bit not0( +//.A(a), +//.B(b)); + +// initial begin +// a = 0; +// #5 +// a = 1; +// #5 $finish; + +// end +//endmodule + module not_9bit( input wire [8:0] A, output wire [8:0] B); @@ -355,6 +724,35 @@ module not_9bit( endmodule +//testbench +//module not_9bit_tb(); +//reg [8:0] a; +//wire [8:0] b; + +// not_9bit not0( +// .A(a), +// .B(b)); + +// initial begin +// a = 9'b000000000; +// #5 +// a = 9'b000000001; +// #5 +// a = 9'b000111000; +// #5 +// a = 9'b010101010; +// #5 +// a = 9'b101010101; +// #5 +// a = 9'b111111111; +// #5 +// a = 9'b100000001; +// #5 $finish; + +// end + +//endmodule + module or_1bit( input wire A, input wire B, @@ -364,6 +762,35 @@ module or_1bit( endmodule +//testbench +//module or_1bit_tb(); +//reg a; +//reg b; +//wire c; + +// or_1bit or0( +// .A(a), +// .B(b), +// .C(c)); + +// initial begin +// a = 0; +// b = 0; +// #5 +// a = 0; +// b = 1; +// #5 +// a = 1; +// b = 0; +// #5 +// a = 1; +// b = 1; +// #5 $finish; + +// end + +//endmodule + module or_9bit( input wire [8:0] A, input wire [8:0] B, @@ -416,6 +843,50 @@ module or_9bit( endmodule +//testbench +//module or_9bit_tb(); +//reg [8:0] a; +//reg [8:0] b; +//wire [8:0] c; + +// or_9bit tb0( +// .A(a), +// .B(b), +// .C(c)); + +// initial begin +// a = 9'b000000000; +// b = 9'b000000000; +// #5 +// a = 9'b111111111; +// b = 9'b111111111; +// #5 +// a = 9'b111111111; +// b = 9'b000000000; +// #5 +// a = 9'b000000000; +// b = 9'b111111111; +// #5 +// a = 9'b000000000; +// b = 9'b111111111; +// #5 +// a = 9'b010101010; +// b = 9'b111111111; +// #5 +// a = 9'b010101010; +// b = 9'b101010101; +// #5 +// a = 9'b000011111; +// b = 9'b111111111; +// #5 +// a = 9'b000000000; +// b = 9'b000010000; +// #5 $finish; + +// end + +//endmodule + module register(input wire clk, reset, input wire [1:0] En, input wire [8:0] Din, @@ -429,54 +900,143 @@ module register(input wire clk, reset, Dout = Din; end else begin - Dout = "ZZZZZZZZZ"; + Dout = 9'bZZZZZZZZZ; end end endmodule -//Mux follows intuitive switching -module mux(input wire [1:0] switch, - input wire [8:0] A,B,C,D, - output reg [8:0] out); - - always @(A,B,C,D,switch) begin - if (switch == 2'b00) begin - out = A; - end - else if (switch == 2'b01) begin - out = B; - end - else if (switch == 2'b10) begin - out = C; - end - else if (switch == 2'b11) begin - out = D; - end - else begin - out = "ZZZZZZZZZ"; - end - end -endmodule +//testbench +//module register_tb(); +//reg clk,reset; +//reg [1:0] En; +//reg [8:0] Din; +//wire [8:0] Dout; + +// register tb0( +// .clk(clk), +// .reset(reset), +// .En(En), +// .Din(Din), +// .Dout(Dout)); + +// initial begin +// clk = 0; +// reset = 0; +// En = 2'b00; +// Din = 9'b000000000; +// #5 +// clk = 1; +// #5 +// clk = 0; +// reset = 0; +// En = 2'b00; +// Din = 9'b010101010; +// #5 +// clk = 1; +// #5 +// clk = 0; +// reset = 1; +// En = 2'b00; +// Din = 9'b010101010; +// #5 +// clk = 1; +// #5 +// clk = 0; +// reset = 0; +// En = 2'b01; +// Din = 9'b101010101; +// #5 +// clk = 1; +// #5 +// clk = 0; +// reset = 0; +// En = 2'b00; +// Din = 9'b000011111; +// #5 +// clk = 1; +// #5 +// clk = 0; +// #5 $finish; + +// end + +//endmodule module shift_logical_left( input wire [8:0] A, output wire [8:0] B); - assign B = {A[7:0],A[8]}; + assign B = {A[7:0],1'b0}; endmodule +//testbench +//module shift_logical_left_tb(); +//reg [8:0] a; +//wire [8:0] b; + +// shift_logical_left tb0( +// .A(a), +// .B(b)); + +// initial begin +// a = 9'b000000000; +// #5 +// a = 9'b000000001; +// #5 +// a = 9'b000111000; +// #5 +// a = 9'b010101010; +// #5 +// a = 9'b101010101; +// #5 +// a = 9'b111111111; +// #5 +// a = 9'b100000001; +// #5 $finish; + +// end + +//endmodule + module shift_logical_right( input wire [8:0] A, output wire [8:0] B); - assign B = {A[0],A[8:1]}; + assign B = {1'b0,A[8:1]}; endmodule +//testbench +//module shift_logical_right_tb(); +//reg [8:0] a; +//wire [8:0] b; + +// shift_logical_right tb0( +// .A(a), +// .B(b)); + +// initial begin +// a = 9'b000000000; +// #5 +// a = 9'b000000001; +// #5 +// a = 9'b000111000; +// #5 +// a = 9'b010101010; +// #5 +// a = 9'b101010101; +// #5 +// a = 9'b111111111; +// #5 +// a = 9'b100000001; +// #5 $finish; + +// end + +//endmodule -// No D instance, fix module sub_9bit( input wire [8:0] A, input wire [8:0] B, @@ -496,6 +1056,50 @@ module sub_9bit( endmodule +//testbench +//module sub_9bit_tb(); +//reg [8:0] a; +//reg [8:0] b; +//wire [8:0] c; + +// sub_9bit tb0( +// .A(a), +// .B(b), +// .C(c)); + +// initial begin +// a = 9'b000000000; +// b = 9'b000000000; +// #5 +// a = 9'b111111111; +// b = 9'b111111111; +// #5 +// a = 9'b111111111; +// b = 9'b000000000; +// #5 +// a = 9'b000000000; +// b = 9'b111111111; +// #5 +// a = 9'b000000000; +// b = 9'b111111111; +// #5 +// a = 9'b010101010; +// b = 9'b111111111; +// #5 +// a = 9'b010101010; +// b = 9'b101010101; +// #5 +// a = 9'b000011111; +// b = 9'b111111111; +// #5 +// a = 9'b000000000; +// b = 9'b000010000; +// #5 $finish; + +// end + +//endmodule + module twos_compliment_9bit( input wire [8:0] A, output wire [8:0] B); @@ -512,4 +1116,33 @@ module twos_compliment_9bit( .Cin(1'b1), .Sum(B)); -endmodule \ No newline at end of file +endmodule + +//testbench +//module twos_compliment_tb(); +//reg [8:0] a; +//wire [8:0] b; + +// twos_compliment_9bit tb0( +// .A(a), +// .B(b)); + +// initial begin +// a = 9'b000000000; +// #5 +// a = 9'b000000001; +// #5 +// a = 9'b000111000; +// #5 +// a = 9'b010101010; +// #5 +// a = 9'b101010101; +// #5 +// a = 9'b111111111; +// #5 +// a = 9'b100000001; +// #5 $finish; + +// end + +//endmodule \ No newline at end of file diff --git a/lab2CA.srcs/sources_1/new/FetchUnit.v b/lab2CA.srcs/sources_1/new/FetchUnit.v index 49ba6a6..7749982 100644 --- a/lab2CA.srcs/sources_1/new/FetchUnit.v +++ b/lab2CA.srcs/sources_1/new/FetchUnit.v @@ -1,7 +1,6 @@ `timescale 1ns / 1ps module FetchUnit(input wire clk, reset, op_idx, - input wire [1:0] write_index, input wire [8:0] AddrIn, output wire [8:0] AddrOut); @@ -11,7 +10,7 @@ module FetchUnit(input wire clk, reset, op_idx, register PC( .clk(clk), .reset(reset), - .En({write_index[0], write_index[1]}), + .En(2'b00), .Din(result_m), .Dout(progC_out)); //Adds 1 to the program counter @@ -19,11 +18,11 @@ module FetchUnit(input wire clk, reset, op_idx, .A(progC_out), .B(1'b1), .Cin(1'b0), - .Sum(result_a)); + .Sum(AddrOut)); mux_2_1 PCmux( .A(AddrIn), - .B(result_a), + .B(AddrOut), .out(result_m), .switch(op_idx)); diff --git a/lab2CA.xpr b/lab2CA.xpr index 1006427..d0d9735 100644 --- a/lab2CA.xpr +++ b/lab2CA.xpr @@ -3,7 +3,7 @@ - + - + @@ -81,7 +81,7 @@ - + @@ -92,6 +92,7 @@ @@ -107,7 +108,6 @@