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Fixed ALU testbench to 4-bit

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WilliamMiceli
2019-03-12 11:12:39 -04:00
parent 9ac8963fb0
commit fe1abc30c5
1 changed files with 8 additions and 8 deletions
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16
lab2CA.srcs/sources_1/new/ALU.v
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@@ -74,7 +74,7 @@ endmodule
module alu_tb(); module alu_tb();
reg [8:0] a; reg [8:0] a;
reg [8:0] b; reg [8:0] b;
reg [2:0] c; reg [3:0] c;
wire [8:0] d; wire [8:0] d;
ALU alu0( ALU alu0(
@@ -86,29 +86,29 @@ module alu_tb();
initial begin initial begin
a = 9'b000000111; a = 9'b000000111;
b = 9'b000111000; b = 9'b000111000;
c = 3'b000; c = 4'b0000;
#5 #5
a = 9'b000011000; a = 9'b000011000;
b = 9'b000011000; b = 9'b000011000;
c = 3'b001; c = 4'b0001;
#5 #5
a = 9'b101010100; a = 9'b101010100;
b = 9'b010101011; b = 9'b010101011;
c = 3'b010; c = 4'b0010;
#5 #5
a = 9'b101010100; a = 9'b101010100;
b = 9'b010101000; b = 9'b010101000;
c = 3'b011; c = 4'b0011;
#5 #5
a = 9'b000110000; a = 9'b000110000;
b = 9'b000111000; b = 9'b000111000;
c = 3'b100; c = 4'b0100;
#5 #5
a = 9'b01011000; a = 9'b01011000;
c = 3'b101; c = 4'b0101;
#5 #5
a = 9'b00001010; a = 9'b00001010;
c = 3'b110; c = 4'b0110;
#5 #5
$finish; $finish;