Fetch Unit label op_idx op_idx AddrIn[8:0] AddrIn[8:0] SIGNEDDECRADIX AddrOut[8:0] AddrOut[8:0] SIGNEDDECRADIX progC_out[8:0] progC_out[8:0] SIGNEDDECRADIX Control Unit label instIn[3:0] instIn[3:0] SIGNEDDECRADIX functBit functBit aluOut[3:0] aluOut[3:0] SIGNEDDECRADIX FU[2:0] FU[2:0] SIGNEDDECRADIX bank[1:0] bank[1:0] SIGNEDDECRADIX addi addi mem mem dataMemEn dataMemEn RegEn RegEn halt halt link link js js Registers label En En write_index[1:0] write_index[1:0] SIGNEDDECRADIX op0_idx[1:0] op0_idx[1:0] SIGNEDDECRADIX op1_idx[1:0] op1_idx[1:0] SIGNEDDECRADIX write_data[8:0] write_data[8:0] SIGNEDDECRADIX op0[8:0] op0[8:0] SIGNEDDECRADIX op1[8:0] op1[8:0] SIGNEDDECRADIX r0_out[8:0] r0_out[8:0] SIGNEDDECRADIX r1_out[8:0] r1_out[8:0] SIGNEDDECRADIX r2_out[8:0] r2_out[8:0] SIGNEDDECRADIX r3_out[8:0] r3_out[8:0] SIGNEDDECRADIX Banks label En En write_index[1:0] write_index[1:0] op0_idx[1:0] op0_idx[1:0] op1_idx[1:0] op1_idx[1:0] write_data[8:0] write_data[8:0] op0[8:0] op0[8:0] op1[8:0] op1[8:0] decOut[3:0] decOut[3:0] r0_out[8:0] r0_out[8:0] SIGNEDDECRADIX r1_out[8:0] r1_out[8:0] SIGNEDDECRADIX r2_out[8:0] r2_out[8:0] SIGNEDDECRADIX r3_out[8:0] r3_out[8:0] SIGNEDDECRADIX Divider label Instruction Memory label address[8:0] address[8:0] SIGNEDDECRADIX readData[8:0] readData[8:0] SIGNEDDECRADIX memory[18:0][8:0] memory[18:0][8:0] SIGNEDDECRADIX switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX switch switch A A B B out out clk clk reset reset En En Din[52:0] Din[52:0] SIGNEDDECRADIX Dout[52:0] Dout[52:0] SIGNEDDECRADIX Data Memory label clk clk writeEnable writeEnable address[8:0] address[8:0] SIGNEDDECRADIX writeData[8:0] writeData[8:0] SIGNEDDECRADIX readData[8:0] readData[8:0] SIGNEDDECRADIX memory[1:0][8:0] memory[1:0][8:0] SIGNEDDECRADIX [1][8:0] [1][8:0] SIGNEDDECRADIX [0][8:0] [0][8:0] SIGNEDDECRADIX Divider label Mux 3 - Addi label switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX Mux 6 - Link label switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX Mux 4 - Mem label switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX Mux 5 - Bank label switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX Divider label op0 - Mux label switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX A[1:0] A[1:0] B[8:0] B[8:0] op1 - Mux label switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX A[1:0] A[1:0] B[8:0] B[8:0] ALU label opcode[3:0] opcode[3:0] SIGNEDDECRADIX operand0[8:0] operand0[8:0] SIGNEDDECRADIX operand1[8:0] operand1[8:0] SIGNEDDECRADIX result[8:0] result[8:0] SIGNEDDECRADIX