`timescale 1ns / 1ps

module add_1bit(
    input wire A,
    input wire B,
    input wire Cin,
    output wire S,
    output wire Cout);

    assign S = (A ^ B) ^ Cin;
    assign Cout = ((A ^ B) & Cin) | (A & B);

endmodule

//testbench
module add1bit_tb();
    reg v;
    reg w;
    reg x;
    wire y;
    wire z;

    add_1bit tb0(
        .A(v),
        .B(w),
        .Cin(x),
        .S(y),
        .Cout(z));
        
    initial begin
        v = 0;
        w = 0;
        x = 0;
        #5
        v = 0;
        w = 1;
        x = 0;
        #5
        v = 0;
        w = 0;
        x = 1;
        #5
        v = 1;
        w = 1;
        x = 0;
        #5
        v = 1;
        w = 1;
        x = 1;
        #5
        $finish;

    end
endmodule

module add_9bit(
    input wire [8:0] A,
    input wire [8:0] B,
    input wire Cin,
    output wire [8:0] Sum,
    output wire Cout);

    wire C_add0;
    wire C_add1;
    wire C_add2;
    wire C_add3;
    wire C_add4;
    wire C_add5;
    wire C_add6;
    wire C_add7;

    add_1bit add0(
        .A(A[0]),
        .B(B[0]),
        .Cin(Cin),
        .S(Sum[0]),
        .Cout(C_add0));

    add_1bit add1(
        .A(A[1]),
        .B(B[1]),
        .Cin(C_add0),
        .S(Sum[1]),
        .Cout(C_add1));
        
    add_1bit add2(
        .A(A[2]),
        .B(B[2]),
        .Cin(C_add1),
        .S(Sum[2]),
        .Cout(C_add2));
        
    add_1bit add3(
        .A(A[3]),
        .B(B[3]),
        .Cin(C_add2),
        .S(Sum[3]),
        .Cout(C_add3));
        
    add_1bit add4(
        .A(A[4]),
        .B(B[4]),
        .Cin(C_add3),
        .S(Sum[4]),
        .Cout(C_add4));
        
    add_1bit add5(
        .A(A[5]),
        .B(B[5]),
        .Cin(C_add4),
        .S(Sum[5]),
        .Cout(C_add5));
        
    add_1bit add6(
        .A(A[6]),
        .B(B[6]),
        .Cin(C_add5),
        .S(Sum[6]),
        .Cout(C_add6));
        
    add_1bit add7(
        .A(A[7]),
        .B(B[7]),
        .Cin(C_add6),
        .S(Sum[7]),
        .Cout(C_add7));
        
    add_1bit add8(
        .A(A[8]),
        .B(B[8]),
        .Cin(C_add7),
        .S(Sum[8]),
        .Cout(Cout));

endmodule

//testbench
module add9bit_tb();
    reg [8:0] a,b;
    reg cin;
    wire [8:0] s;
    wire cout;

    add_9bit tb0(
        .A(a),
        .B(b),
        .Cin(cin),
        .Sum(s),
        .Cout(cout));
    
    
    initial begin
        a = 9'b000000000;
        b = 9'b000000000;
        cin = 0;
        #5
        a = 9'b000000001;
        b = 9'b000000000;
        cin = 0;
        #5
        a = 9'b000000000;
        b = 9'b000000001;
        cin = 1;
        #5
        a = 9'b000000001;
        b = 9'b000000001;
        cin = 0;
        #5
        a = 9'b000001000;
        b = 9'b000000001;
        cin = 1;
    end
endmodule

module and_1bit(
    input wire A,
    input wire B,
    output wire C);

    assign C = A & B;

endmodule

//testbench
module and1bit_tb();
    reg a,b;
    wire c;

    and_1bit and0(
        .A(a),
        .B(b),
        .C(c));
    
    initial begin
        a = 0;
        b = 0;
        #5
        a = 0;
        b = 1;
        #5
        a = 1;
        b = 0;
        #5
        a = 1;
        b = 1;
        #5
        $finish;

    end
endmodule

module and_9bit(
    input wire [8:0] A,
    input wire [8:0] B,
    output wire [8:0] C);

    and_1bit and0(
        .A(A[0]),
        .B(B[0]),
        .C(C[0]));

    and_1bit and1(
        .A(A[1]),
        .B(B[1]),
        .C(C[1]));
        
    and_1bit and2(
        .A(A[2]),
        .B(B[2]),
        .C(C[2]));
        
    and_1bit and3(
        .A(A[3]),
        .B(B[3]),
        .C(C[3]));
        
    and_1bit and4(
        .A(A[4]),
        .B(B[4]),
        .C(C[4]));
    
    and_1bit and5(
        .A(A[5]),
        .B(B[5]),
        .C(C[5]));
        
    and_1bit and6(
        .A(A[6]),
        .B(B[6]),
        .C(C[6]));
        
    and_1bit and7(
        .A(A[7]),
        .B(B[7]),
        .C(C[7]));
        
    and_1bit and8(
        .A(A[8]),
        .B(B[8]),
        .C(C[8]));

endmodule

//testbench
module and9bit_tb();
    reg [8:0] a,b;
    wire [8:0] c;

    and_9bit and0(
        .A(a),
        .B(b),
        .C(c));
    
    initial begin
        a = 9'b000000000;
        b = 9'b000000000;
        #5
        a = 9'b000000000;
        b = 9'b000000001;
        #5
        a = 9'b000000001;
        b = 9'b000000000;
        #5
        a = 9'b000000001;
        b = 9'b000000001;
        #5
        a = 9'b000100001;
        b = 9'b000000001;
        #5
        a = 9'b000100001;
        b = 9'b000100001;
        #5
        $finish;

    end
endmodule

module gen_clock();
    reg clk;
    initial begin
        clk = 1'b0;
    end
    always begin
        #5 clk = ~clk; // Period to be determined
    end
endmodule

module mux_2_1 tb0(
    input wire switch,
    input wire [8:0] A,B,
    output reg [8:0] out);
           
    always @(A,B,switch) begin
        case (switch)
            1'b0 : out = A;
            1'b1 : out = B;
            default : out = 9'bxxxxxxxxx;
        endcase
    end
endmodule

//testbench
module mux_2_1_tb();
    reg s;
    reg [8:0] a,b;
    wire [8:0] c;

    mux_2_1 tb0(
        .switch(s),
        .A(a),
        .B(b),
        .out(c));
    
    initial begin
        s = 0;
        a = 9'b000000101;
        b = 9'b000000000;
        #5
        s = 1;
        a = 9'b000000001;
        b = 9'b000100001;
        #5
        s = 0;
        a = 9'b000000000;
        b = 9'b000000001;
        #5
        s = 1;
        a = 9'b000000001;
        b = 9'b000000001;
        #5
        s = 0;
        a = 9'b000010001;
        b = 9'b000000001;
        #5
        s = 1;
        a = 9'b000010001;
        b = 9'b000010111;
        #5
        $finish;

    end
endmodule

module mux_4_1(input wire [1:0] switch,
           input wire [8:0] A,B,C,D,
           output reg [8:0] out);
           
    always @(A,B,C,D,switch) begin
        case (switch)
            2'b00 : out = A;
            2'b01 : out = B;
            2'b10 : out = C;
            2'b11 : out = D;
            default : out = 9'bxxxxxxxxx;
        endcase
    end

endmodule

//testbench
module mux_4_1_tb();
    reg [1:0] s;
    reg [8:0] a,b,c,d;
    wire [8:0] e;

    mux_4_1 tb0(
        .switch(s),
        .A(a),
        .B(b),
        .C(c),
        .D(d),
        .out(e));
    
    initial begin
        s = 2'b00;
        a = 9'b000000101;
        b = 9'b000111100;
        c = 9'b001001001;
        d = 9'b100000000;
        #5
        s = 2'b01;
        a = 9'b000000101;
        b = 9'b000111100;
        c = 9'b001001001;
        d = 9'b100000000;
        #5
        s = 2'b10;
        a = 9'b000000101;
        b = 9'b000111100;
        c = 9'b001001001;
        d = 9'b100000000;
        #5
        s = 2'b11;
        a = 9'b000000101;
        b = 9'b000111100;
        c = 9'b001001001;
        d = 9'b100000000;
        #5
        $finish;

    end
endmodule

module mux_8_1(
    input wire [2:0] switch,
    input wire [8:0] A,B,C,D,E,F,G,H,
    output reg [8:0] out);
           
    always @(A,B,C,D,E,F,G,H,switch) begin
        case (switch)
            3'b000 : out = A;
            3'b001 : out = B;
            3'b010 : out = C;
            3'b011 : out = D;
            3'b100 : out = E;
            3'b101 : out = F;
            3'b110 : out = G;
            3'b111 : out = H;
            default : out = 9'bxxxxxxxxx;
        endcase
    end
endmodule

//testbench
module mux_8_1_tb();
    reg [2:0] s;
    reg [8:0] a,b,c,d,e,f,g,h;
    wire [8:0] out;

    mux_8_1 tb0(
        .switch(s),
        .A(a),
        .B(b),
        .C(c),
        .D(d),
        .E(e),
        .F(f),
        .G(g),
        .H(h),
        .out(out));
    
    initial begin
        s = 3'b000;
        a = 9'b000000101;
        b = 9'b000111100;
        c = 9'b001001001;
        d = 9'b100110000;
        e = 9'b010000101;
        f = 9'b010111100;
        g = 9'b011001001;
        h = 9'b111000000;
        #5
        s = 3'b001;
        #5
        s = 3'b010;
        #5
        s = 3'b011;
        #5
        s = 3'b100;
        #5
        s = 3'b101;
        #5
        s = 3'b110;
        #5
        s = 3'b111;
        #5
        $finish;

    end
endmodule

module nor_1bit(
    input wire A,
    input wire B,
    output wire C);
    
    //assign C = A |~ B;
    assign C = ~(A | B);

endmodule

//testbench
module nor_1bit_tb();
    reg a;
    reg b;
    wire c;

    nor_1bit nor0(
        .A(a),
        .B(b),
        .C(c));
    
    initial begin
        a = 0;
        b = 0;
        #5
        a = 0;
        b = 1;
        #5
        a = 1;
        b = 0;
        #5
        a = 1;
        b = 1;
        #5
        $finish;

    end
endmodule

module nor_9bit(
    input wire [8:0] A,
    input wire [8:0] B,
    output wire [8:0] C);
    
    nor_1bit nor0(
        .A(A[0]),
        .B(B[0]),
        .C(C[0]));
        
    nor_1bit nor1(
        .A(A[1]),
        .B(B[1]),
        .C(C[1]));
        
    nor_1bit nor2(
        .A(A[2]),
        .B(B[2]),
        .C(C[2]));
        
    nor_1bit nor3(
        .A(A[3]),
        .B(B[3]),
        .C(C[3]));
        
    nor_1bit nor4(
        .A(A[4]),
        .B(B[4]),
        .C(C[4]));
        
    nor_1bit nor5(
        .A(A[5]),
        .B(B[5]),
        .C(C[5]));
        
    nor_1bit nor6(
        .A(A[6]),
        .B(B[6]),
        .C(C[6]));
        
    nor_1bit nor7(
        .A(A[7]),
        .B(B[7]),
        .C(C[7]));
        
    nor_1bit nor8(
        .A(A[8]),
        .B(B[8]),
        .C(C[8]));

endmodule

//testbench
module nor_9bit_tb();
    reg [8:0] a;
    reg [8:0] b;
    wire [8:0] c;

    nor_9bit nor0(
        .A(a),
        .B(b),
        .C(c));
    
    initial begin
        a = 9'b000000000;
        b = 9'b000000000;
        #5
        a = 9'b000000000;
        b = 9'b000000001;
        #5
        a = 9'b000000001;
        b = 9'b000000000;
        #5
        a = 9'b000000001;
        b = 9'b000000001;
        #5
        a = 9'b000100001;
        b = 9'b000000001;
        #5
        a = 9'b000100001;
        b = 9'b000100001;
        #5
        $finish;

    end
endmodule


module not_1bit(
    input wire A,
    output wire B);
    
    assign B = ~A;

endmodule

//testbench
module not_1bit_tb();
    reg a;
    wire b;

    not_1bit not0(
        .A(a),
        .B(b));
        
    initial begin
        a = 0;
        #5
        a = 1;
        #5
        $finish;

    end
endmodule

module not_9bit(
    input wire [8:0] A,
    output wire [8:0] B);

    not_1bit not0(
        .A(A[0]),
        .B(B[0]));

    not_1bit not1(
        .A(A[1]),
        .B(B[1]));
        
    not_1bit not2(
        .A(A[2]),
        .B(B[2]));
        
    not_1bit not3(
        .A(A[3]),
        .B(B[3]));
        
    not_1bit not4(
        .A(A[4]),
        .B(B[4]));
        
    not_1bit not5(
        .A(A[5]),
        .B(B[5]));
        
    not_1bit not6(
        .A(A[6]),
        .B(B[6]));
        
    not_1bit not7(
        .A(A[7]),
        .B(B[7]));
        
    not_1bit not8(
        .A(A[8]),
        .B(B[8]));

endmodule

//testbench
module not_9bit_tb();
    reg [8:0] a;
    wire [8:0] b;

    not_9bit not0(
        .A(a),
        .B(b));
    
    initial begin
        a = 9'b000000000;
        #5
        a = 9'b000000001;
        #5
        a = 9'b000111000;
        #5
        a = 9'b010101010;
        #5
        a = 9'b101010101;
        #5
        a = 9'b111111111;
        #5
        a = 9'b100000001;
        #5
        $finish;

    end
endmodule

module or_1bit(
    input wire A,
    input wire B,
    output wire C);
    
    assign C = A | B;

endmodule

//testbench
module or_1bit_tb();
    reg a;
    reg b;
    wire c;

    or_1bit or0(
        .A(a),
        .B(b),
        .C(c));
    
    initial begin
        a = 0;
        b = 0;
        #5
        a = 0;
        b = 1;
        #5
        a = 1;
        b = 0;
        #5
        a = 1;
        b = 1;
        #5
        $finish;

    end
endmodule

module or_9bit(
    input wire [8:0] A,
    input wire [8:0] B,
    output wire [8:0] C);
    
    or_1bit or0(
        .A(A[0]),
        .B(B[0]),
        .C(C[0]));
        
    or_1bit or1(
        .A(A[1]),
        .B(B[1]),
        .C(C[1]));
        
    or_1bit or2(
        .A(A[2]),
        .B(B[2]),
        .C(C[2]));
        
    or_1bit or3(
        .A(A[3]),
        .B(B[3]),
        .C(C[3]));
        
    or_1bit or4(
        .A(A[4]),
        .B(B[4]),
        .C(C[4]));
        
    or_1bit or5(
        .A(A[5]),
        .B(B[5]),
        .C(C[5]));
        
    or_1bit or6(
        .A(A[6]),
        .B(B[6]),
        .C(C[6]));
        
    or_1bit or7(
        .A(A[7]),
        .B(B[7]),
        .C(C[7]));
        
    or_1bit or8(
        .A(A[8]),
        .B(B[8]),
        .C(C[8]));

endmodule

//testbench
module or_9bit_tb();
    reg [8:0] a;
    reg [8:0] b;
    wire [8:0] c;

    or_9bit tb0(
        .A(a),
        .B(b),
        .C(c));
    
    initial begin
        a = 9'b000000000;
        b = 9'b000000000;
        #5
        a = 9'b111111111;
        b = 9'b111111111;
        #5
        a = 9'b111111111;
        b = 9'b000000000;
        #5
        a = 9'b000000000;
        b = 9'b111111111;
        #5
        a = 9'b000000000;
        b = 9'b111111111;
        #5
        a = 9'b010101010;
        b = 9'b111111111;
        #5
        a = 9'b010101010;
        b = 9'b101010101;
        #5
        a = 9'b000011111;
        b = 9'b111111111;
        #5
        a = 9'b000000000;
        b = 9'b000010000;
        #5
        $finish;

    end
endmodule

module register(
    input wire clk, reset,
    input wire [1:0] En,
    input wire [8:0] Din,
    output reg [8:0] Dout);
                
    always @(posedge clk) begin
        if (reset == 1'b1) begin
            Dout = 9'b000000000;
        end
        else if (En == 2'b00) begin
            Dout = Din;
        end
        else begin
        Dout = Dout;
        end
    end
endmodule

//testbench
module register_tb();
    reg clk,reset;
    reg [1:0] En;
    reg [8:0] Din;
    wire [8:0] Dout;

    register tb0(
        .clk(clk),
        .reset(reset),
        .En(En),
        .Din(Din),
        .Dout(Dout));
    
    initial begin
        clk = 0;
        reset = 0;
        En = 2'b00;
        Din = 9'b000000000;
        #5
        clk = 1;
        #5
        clk = 0;
        reset = 0;
        En = 2'b00;
        Din = 9'b010101010;
        #5
        clk = 1;
        #5
        clk = 0;
        reset = 1;
        En = 2'b00;
        Din = 9'b010101010;
        #5
        clk = 1;
        #5
        clk = 0;
        reset = 0;
        En = 2'b01;
        Din = 9'b101010101;
        #5
        clk = 1;
        #5
        clk = 0;
        reset = 0;
        En = 2'b00;
        Din = 9'b000011111;
        #5
        clk = 1;
        #5
        clk = 0;
        #5
        $finish;

    end
endmodule 
    
module shift_logical_left(
    input wire [8:0] A,
    output wire [8:0] B);
    
    assign B = {A[7:0],1'b0};

endmodule

//testbench
module shift_logical_left_tb();
    reg [8:0] a;
    wire [8:0] b;

    shift_logical_left tb0(
        .A(a),
        .B(b));
    
    initial begin
        a = 9'b000000000;
        #5
        a = 9'b000000001;
        #5
        a = 9'b000111000;
        #5
        a = 9'b010101010;
        #5
        a = 9'b101010101;
        #5
        a = 9'b111111111;
        #5
        a = 9'b100000001;
        #5
        $finish;

    end
endmodule

module shift_logical_right(
    input wire [8:0] A,
    output wire [8:0] B);
    
    assign B = {1'b0,A[8:1]};

endmodule

//testbench
module shift_logical_right_tb();
    reg [8:0] a;
    wire [8:0] b;

    shift_logical_right tb0(
        .A(a),
        .B(b));

    initial begin
        a = 9'b000000000;
        #5
        a = 9'b000000001;
        #5
        a = 9'b000111000;
        #5
        a = 9'b010101010;
        #5
        a = 9'b101010101;
        #5
        a = 9'b111111111;
        #5
        a = 9'b100000001;
        #5
        $finish;

    end
endmodule

module sub_9bit(
    input wire [8:0] A,
    input wire [8:0] B,
    output wire [8:0] C);
    
    wire [8:0] D;
    
    twos_compliment_9bit two_comp0(
        .A(B),
        .B(D));
    
    add_9bit add0(
        .A(A),
        .B(D),
        .Cin(1'b0),
        .Sum(C));

endmodule

//testbench
module sub_9bit_tb();
    reg [8:0] a;
    reg [8:0] b;
    wire [8:0] c;

    sub_9bit tb0(
        .A(a),
        .B(b),
        .C(c));
    
    initial begin
        a = 9'b000000000;
        b = 9'b000000000;
        #5
        a = 9'b111111111;
        b = 9'b111111111;
        #5
        a = 9'b111111111;
        b = 9'b000000000;
        #5
        a = 9'b000000000;
        b = 9'b111111111;
        #5
        a = 9'b000000000;
        b = 9'b111111111;
        #5
        a = 9'b010101010;
        b = 9'b111111111;
        #5
        a = 9'b010101010;
        b = 9'b101010101;
        #5
        a = 9'b000011111;
        b = 9'b111111111;
        #5
        a = 9'b000000000;
        b = 9'b000010000;
        #5
        $finish;

    end
endmodule

module twos_compliment_9bit(
    input wire [8:0] A,
    output wire [8:0] B);
    
    wire [8:0] C;
    
    not_9bit not0(
        .A(A),
        .B(C));
        
    add_9bit add0(
        .A(C),
        .B(9'b000000000),
        .Cin(1'b1),
        .Sum(B));

endmodule

//testbench
module twos_compliment_tb();
    reg [8:0] a;
    wire [8:0] b;

    twos_compliment_9bit tb0(
        .A(a),
        .B(b));
    
    initial begin
        a = 9'b000000000;
        #5
        a = 9'b000000001;
        #5
        a = 9'b000111000;
        #5
        a = 9'b010101010;
        #5
        a = 9'b101010101;
        #5
        a = 9'b111111111;
        #5
        a = 9'b100000001;
        #5
        $finish;

    end
endmodule