Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date             : Wed Mar 13 11:13:48 2019
| Host             : DESKTOP-CSFKQTV running 64-bit major release  (build 9200)
| Command          : report_power -file CPU9bits_power_routed.rpt -pb CPU9bits_power_summary_routed.pb -rpx CPU9bits_power_routed.rpx
| Design           : CPU9bits
| Device           : xc7k160tifbg484-2L
| Design State     : routed
| Grade            : industrial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 0.084        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 0.000        |
| Device Static (W)        | 0.084        |
| Effective TJA (C/W)      | 2.5          |
| Max Ambient (C)          | 99.8         |
| Junction Temperature (C) | 25.2         |
| Confidence Level         | High         |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------+-----------+----------+-----------+-----------------+
| On-Chip      | Power (W) | Used     | Available | Utilization (%) |
+--------------+-----------+----------+-----------+-----------------+
| Slice Logic  |     0.000 |        1 |       --- |             --- |
|   Others     |     0.000 |        1 |       --- |             --- |
| I/O          |     0.000 |        1 |       285 |            0.35 |
| Static Power |     0.084 |          |           |                 |
| Total        |     0.084 |          |           |                 |
+--------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       0.950 |     0.023 |       0.000 |      0.023 |
| Vccaux    |       1.800 |     0.016 |       0.000 |      0.016 |
| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       0.950 |     0.001 |       0.000 |      0.001 |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.018 |       0.000 |      0.018 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+------------------------------------------------+--------+
| User Input Data             | Confidence | Details                                        | Action |
+-----------------------------+------------+------------------------------------------------+--------+
| Design implementation state | High       | Design is routed                               |        |
| Clock nodes activity        | High       | User specified more than 95% of clocks         |        |
| I/O nodes activity          | High       | User specified more than 95% of inputs         |        |
| Internal nodes activity     | High       | User specified more than 25% of internal nodes |        |
| Device models               | High       | Device models are Production                   |        |
|                             |            |                                                |        |
| Overall confidence level    | High       |                                                |        |
+-----------------------------+------------+------------------------------------------------+--------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 2.5                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 4.2                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+------+-----------+
| Name | Power (W) |
+------+-----------+