Fetch Unit label clk clk reset reset op_idx op_idx AddrIn[8:0] AddrIn[8:0] AddrOut[8:0] AddrOut[8:0] progC_out[8:0] progC_out[8:0] result_m[8:0] result_m[8:0] cout cout Control Unit label instIn[3:0] instIn[3:0] functBit functBit aluOut[3:0] aluOut[3:0] FU[2:0] FU[2:0] bank[1:0] bank[1:0] addi addi mem mem dataMemEn dataMemEn RegEn RegEn halt halt link link js js Divider label Instruction Memory label address[8:0] address[8:0] UNSIGNEDDECRADIX readData[8:0] readData[8:0] BINARYRADIX memory[8:0][8:0] memory[8:0][8:0] RF label clk clk reset reset En En write_index[1:0] write_index[1:0] UNSIGNEDDECRADIX op0_idx[1:0] op0_idx[1:0] UNSIGNEDDECRADIX op1_idx[1:0] op1_idx[1:0] UNSIGNEDDECRADIX write_data[8:0] write_data[8:0] UNSIGNEDDECRADIX op0[8:0] op0[8:0] UNSIGNEDDECRADIX op1[8:0] op1[8:0] UNSIGNEDDECRADIX r0_out[8:0] r0_out[8:0] UNSIGNEDDECRADIX r1_out[8:0] r1_out[8:0] UNSIGNEDDECRADIX r2_out[8:0] r2_out[8:0] UNSIGNEDDECRADIX r3_out[8:0] r3_out[8:0] UNSIGNEDDECRADIX