clk clk reset reset done done clk clk address[8:0] address[8:0] UNSIGNEDDECRADIX readData[8:0] readData[8:0] enable enable write_index[1:0] write_index[1:0] op0[8:0] op0[8:0] op1[8:0] op1[8:0] r0_out[8:0] r0_out[8:0] UNSIGNEDDECRADIX r1_out[8:0] r1_out[8:0] UNSIGNEDDECRADIX r2_out[8:0] r2_out[8:0] UNSIGNEDDECRADIX r3_out[8:0] r3_out[8:0] UNSIGNEDDECRADIX enable enable write_index[1:0] write_index[1:0] op0_idx[1:0] op0_idx[1:0] write_data[8:0] write_data[8:0] op0[8:0] op0[8:0] r0_out[8:0] r0_out[8:0] UNSIGNEDDECRADIX r1_out[8:0] r1_out[8:0] r2_out[8:0] r2_out[8:0] UNSIGNEDDECRADIX r3_out[8:0] r3_out[8:0] AddrIn[8:0] AddrIn[8:0] AddrOut[8:0] AddrOut[8:0] UNSIGNEDDECRADIX progC_out[8:0] progC_out[8:0] result_m[8:0] result_m[8:0] A[8:0] A[8:0] B[8:0] B[8:0] Sum[8:0] Sum[8:0] addi addi A[2:0] A[2:0] B[8:0] B[8:0]