Program Counter label clk clk reset reset En En Din[8:0] Din[8:0] UNSIGNEDDECRADIX Dout[8:0] Dout[8:0] UNSIGNEDDECRADIX Fetch Unit label op_idx op_idx AddrIn[8:0] AddrIn[8:0] UNSIGNEDDECRADIX AddrOut[8:0] AddrOut[8:0] UNSIGNEDDECRADIX progC_out[8:0] progC_out[8:0] result_m[8:0] result_m[8:0] cout cout Control Unit label instIn[3:0] instIn[3:0] functBit functBit aluOut[3:0] aluOut[3:0] FU[2:0] FU[2:0] bank[1:0] bank[1:0] addi addi mem mem dataMemEn dataMemEn RegEn RegEn halt halt link link js js Registers label En En write_index[1:0] write_index[1:0] UNSIGNEDDECRADIX op0_idx[1:0] op0_idx[1:0] UNSIGNEDDECRADIX op1_idx[1:0] op1_idx[1:0] UNSIGNEDDECRADIX write_data[8:0] write_data[8:0] UNSIGNEDDECRADIX op0[8:0] op0[8:0] UNSIGNEDDECRADIX op1[8:0] op1[8:0] UNSIGNEDDECRADIX decOut[3:0] decOut[3:0] UNSIGNEDDECRADIX r0_out[8:0] r0_out[8:0] SIGNEDDECRADIX r1_out[8:0] r1_out[8:0] SIGNEDDECRADIX r2_out[8:0] r2_out[8:0] SIGNEDDECRADIX r3_out[8:0] r3_out[8:0] SIGNEDDECRADIX Banks label En En write_index[1:0] write_index[1:0] op0_idx[1:0] op0_idx[1:0] op1_idx[1:0] op1_idx[1:0] write_data[8:0] write_data[8:0] op0[8:0] op0[8:0] op1[8:0] op1[8:0] decOut[3:0] decOut[3:0] r0_out[8:0] r0_out[8:0] SIGNEDDECRADIX r1_out[8:0] r1_out[8:0] SIGNEDDECRADIX r2_out[8:0] r2_out[8:0] SIGNEDDECRADIX r3_out[8:0] r3_out[8:0] SIGNEDDECRADIX ALU label opcode[3:0] opcode[3:0] operand0[8:0] operand0[8:0] SIGNEDDECRADIX operand1[8:0] operand1[8:0] SIGNEDDECRADIX result[8:0] result[8:0] SIGNEDDECRADIX result_A[8:0] result_A[8:0] SIGNEDDECRADIX result_B[8:0] result_B[8:0] SIGNEDDECRADIX result_C[8:0] result_C[8:0] SIGNEDDECRADIX result_D[8:0] result_D[8:0] SIGNEDDECRADIX result_E[8:0] result_E[8:0] SIGNEDDECRADIX result_F[8:0] result_F[8:0] SIGNEDDECRADIX result_G[8:0] result_G[8:0] SIGNEDDECRADIX result_H[8:0] result_H[8:0] SIGNEDDECRADIX result_I[8:0] result_I[8:0] SIGNEDDECRADIX result_J[8:0] result_J[8:0] SIGNEDDECRADIX result_K[8:0] result_K[8:0] SIGNEDDECRADIX result_L[8:0] result_L[8:0] SIGNEDDECRADIX result_M[8:0] result_M[8:0] SIGNEDDECRADIX result_N[8:0] result_N[8:0] SIGNEDDECRADIX result_O[8:0] result_O[8:0] SIGNEDDECRADIX result_P[8:0] result_P[8:0] SIGNEDDECRADIX cout cout EM Module label reset reset clk clk PipIn[50:0] PipIn[50:0] PipOut[61:0] PipOut[61:0] instr[8:0] instr[8:0] op1[8:0] op1[8:0] op0[8:0] op0[8:0] FUAddr[8:0] FUAddr[8:0] FUJB[8:0] FUJB[8:0] PCout[8:0] PCout[8:0] JBRes[8:0] JBRes[8:0] FUJ[8:0] FUJ[8:0] FUB[8:0] FUB[8:0] AddiOut[8:0] AddiOut[8:0] AluOut[8:0] AluOut[8:0] RFIn[8:0] RFIn[8:0] dataMemOut[8:0] dataMemOut[8:0] SE1N[8:0] SE1N[8:0] SE2N[8:0] SE2N[8:0] SE3N[8:0] SE3N[8:0] bankOP[8:0] bankOP[8:0] jumpNeg[8:0] jumpNeg[8:0] aluOp[3:0] aluOp[3:0] FU[2:0] FU[2:0] bankS[1:0] bankS[1:0] addiS addiS RegEn RegEn loadS loadS fetchBranch fetchBranch cout0 cout0 cout1 cout1 link link js js dataMemEn dataMemEn Divider label Instruction Memory label address[8:0] address[8:0] UNSIGNEDDECRADIX readData[8:0] readData[8:0] BINARYRADIX memory[100:0][8:0] memory[100:0][8:0] switch switch A[8:0] A[8:0] B[8:0] B[8:0] out[8:0] out[8:0] switch switch A A B B out out clk clk reset reset En En Din[50:0] Din[50:0] Dout[50:0] Dout[50:0] Data Memory label clk clk writeEnable writeEnable address[8:0] address[8:0] UNSIGNEDDECRADIX writeData[8:0] writeData[8:0] readData[8:0] readData[8:0] memory[100:0][8:0] memory[100:0][8:0] Divider label Mux 3 label switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX Mux 4 label switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX Mux 5 label switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX Mux 6 label switch switch A[8:0] A[8:0] SIGNEDDECRADIX B[8:0] B[8:0] SIGNEDDECRADIX out[8:0] out[8:0] SIGNEDDECRADIX Pipe 2 label clk clk reset reset En En Din[61:0] Din[61:0] Dout[61:0] Dout[61:0]