`timescale 1ns / 1ps


module FetchUnit(input wire clk, reset, op_idx,
                 input wire [1:0] write_index,
                 input wire [8:0] AddrIn,
                 output wire [8:0] AddrOut);
  
    //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) 
    wire [8:0] progC_out, result_a, result_m;
    
    register PC(
        .clk(clk),
        .reset(reset),
        .En({write_index[0], write_index[1]}),
        .Din(result_m),
        .Dout(progC_out));
    //Adds 1 to the program counter
    add_9bit PCAdder(
        .A(progC_out),
        .B(1'b1),
        .Cin(1'b0),
        .Sum(result_a));
        
    mux_2_1 PCmux(
        .A(AddrIn),
        .B(result_a),
        .out(result_m),
        .switch(op_idx));
        
        
endmodule