`timescale 1ns / 1ps

module WMUdule(
        input wire [61:0] PipIn,
        output wire [8:0] RFIn,FUAddr,
        output wire [1:0] instr,
        output wire fetchBranch, RegEn
        );
        
        wire [8:0] PCout,AddiOut,AluOut,dataMemOut,bankOP,loadMux,linkData,bankData;
        wire addiS,loadS,link,bankS;
        
        assign RegEn = PipIn[61];
        assign PCout = PipIn[60:52];
        assign bankOP = PipIn[51:43];
        assign FUAddr = PipIn[42:34];
        assign AluOut = PipIn[33:25];
        assign dataMemOut = PipIn[24:16];
        assign AddiOut = PipIn[15:7];
        assign instr = PipIn[6:5];
        assign bankS = PipIn[4];
        assign loadS = PipIn[3];
        assign link = PipIn[2];
        assign addiS = PipIn[1];
        assign fetchBranch = PipIn[0];
    
     mux_2_1 mux3(
        .A(AluOut),
        .B(AddiOut),
        .out(loadMux),
        .switch(addiS)
    );
    
    mux_2_1 mux4(
        .A(linkData),
        .B(dataMemOut), // This is DATA MEM
        .out(bankData),
        .switch(loadS)
    );

    ///--------------------------Bank stuff

    mux_2_1 mux5(
        .A(bankData),
        .B(bankOP), 
        .out(RFIn),
        .switch(bankS)
    );

    ///--------------------------Link Stuff

    mux_2_1 mux6(
        .A(loadMux),
        .B(PCout),
        .out(linkData),
        .switch(link)
    );
endmodule

//module WMUdule_tb();
//    reg [61:0] PipIn;
//    wire [8:0] RFIn,FUAddr;
//    wire [1:0] instr;
//    wire fetchBranch, RegEn;

//    WMUdule WMUdule_0(
//        .PipIn(PipIn),
//        .RFIn(RFIn),
//        .FUAddr(FUAddr),
//        .instr(instr),
//        .fetchBranch(fetchBranch),
//        .RegEn(RegEn)
//        );
    
//    initial begin
//        PipIn = 1;
//        #5
//        $finish;

//    end
//endmodule