`timescale 1ns / 1ps

module ALU(
    input wire [2:0] opcode,
    input wire [8:0] operand0,
    input wire [8:0] operand1,
    output wire [8:0] result 
    );
    
    // Wires for connecting the modules to the mux
    wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H;
    
    // A (000) - Add
    adder_9bit(
        .A(operand0),
        .B(operand1),
        .Cin(1'b0),
        .Sum(result_A));
    // B (001) - Subtract
    // C (010) - OR
    // D (011) - NOR
    // E (100) - AND
    // F (101) - Shift Logical Left
    // G (110) - Shift Logical Right
    // H (111)
    
    
    // MUX chooses which result to show based on the OPCODE
    mux_8_1 mux_result(
        .switch(opcode),
        .A(result_A),
        .B(result_B),
        .C(result_C),
        .D(result_D),
        .E(result_E),
        .F(result_F),
        .G(result_G),
        .H(result_H),
        .out(result));

endmodule