clk clk reset reset done done instr[8:0] instr[8:0] AddrOut[8:0] AddrOut[8:0] r0_out[8:0] r0_out[8:0] r1_out[8:0] r1_out[8:0] r2_out[8:0] r2_out[8:0] r3_out[8:0] r3_out[8:0] r0_out[8:0] r0_out[8:0] r1_out[8:0] r1_out[8:0] r2_out[8:0] r2_out[8:0] r3_out[8:0] r3_out[8:0] switch switch writeEnable writeEnable address[8:0] address[8:0] writeData[8:0] writeData[8:0] memory[15:0][8:0] memory[15:0][8:0] readData[8:0] readData[8:0] operand0[8:0] operand0[8:0] result_K[8:0] result_K[8:0] op_idx op_idx AddrIn[8:0] AddrIn[8:0] progC_out[8:0] progC_out[8:0] result_m[8:0] result_m[8:0] cout cout result[8:0] result[8:0] switch[3:0] switch[3:0] K[8:0] K[8:0] out[8:0] out[8:0] FU[2:0] FU[2:0]