Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec  6 23:38:27 MST 2018
| Date         : Sun Mar 24 12:14:36 2019
| Host         : DESKTOP-CSFKQTV running 64-bit major release  (build 9200)
| Command      : report_methodology -file CPU9bits_methodology_drc_routed.rpt -pb CPU9bits_methodology_drc_routed.pb -rpx CPU9bits_methodology_drc_routed.rpx
| Design       : CPU9bits
| Device       : xc7k160tifbg484-2L
| Speed File   : -2L
| Design State : Fully Routed
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Report Methodology

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
             Max violations: <unlimited>
             Violations found: 5
+-----------+----------+-----------------------------+------------+
| Rule      | Severity | Description                 | Violations |
+-----------+----------+-----------------------------+------------+
| TIMING-17 | Warning  | Non-clocked sequential cell | 5          |
+-----------+----------+-----------------------------+------------+

2. REPORT DETAILS
-----------------
TIMING-17#1 Warning
Non-clocked sequential cell  
The clock pin FetchU/PC/Dout_reg[0]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#2 Warning
Non-clocked sequential cell  
The clock pin FetchU/PC/Dout_reg[1]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#3 Warning
Non-clocked sequential cell  
The clock pin FetchU/PC/Dout_reg[2]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#4 Warning
Non-clocked sequential cell  
The clock pin FetchU/PC/Dout_reg[3]/C is not reached by a timing clock
Related violations: <none>

TIMING-17#5 Warning
Non-clocked sequential cell  
The clock pin FetchU/PC/Dout_reg[4]/C is not reached by a timing clock
Related violations: <none>