`timescale 1ns / 1ps



module lab2testing();
endmodule

module regFile(input wire clk, reset,
                input wire [1:0] write_index, op0_idx, op1_idx,
                input wire [8:0] write_data,
                output wire [8:0] op0, op1);
    
    wire [8:0] r0_out, r1_out, r2_out, r3_out;
    
    // To select a register En input must be 2'b00
    
    register r0(
        .clk(clk),
        .reset(reset),
        .En({write_index[0], write_index[1]}),
        .Din(write_data),
        .Dout(r0_out));
        
    register r1(
        .clk(clk),
        .reset(reset),
        .En({write_index[0], ~write_index[1]}),
        .Din(write_data),
        .Dout(r1_out));
        
    register r2(
        .clk(clk),
        .reset(reset),
        .En({~write_index[0], write_index[1]}),
        .Din(write_data),
        .Dout(r2_out));
        
    register r3(
        .clk(clk),
        .reset(reset),
        .En({~write_index[0], ~write_index[1]}),
        .Din(write_data),
        .Dout(r3_out));    
        
    Mux m0(
        .A(r0_out),
        .B(r1_out),
        .C(r2_out),
        .D(r3_out),
        .switch(op0_idx));
        
    Mux m1(
        .A(r0_out),
        .B(r1_out),
        .C(r2_out),
        .D(r3_out),
        .switch(op1_idx));
    
<<<<<<< Updated upstream
endmodule
=======
endmodule

module register(input wire clk, reset,
                input wire [1:0] En,
                input wire [7:0] Din,
                output reg [7:0] Dout);

endmodule

module MUX();

endmodule

module fetchUnit(input wire clk, reset, write_en);
    register progcount(
        .clk(clk),
        .reset(reset),
        .En(),
        .Din(),
        .Dout());

endmodule
>>>>>>> Stashed changes