`timescale 1ns / 1ps

module ControlUnit(
    input wire [3:0] instIn,
    input wire functBit,
    output reg [2:0] aluOut,
    output reg [2:0] FU,
    output reg addi,
    output reg mem,
    output reg load,
    output reg RegEn
    );
    
        always @(instIn)begin
            case(instIn)
            4'b0101:
                if(functBit == 1) begin
                    aluOut <= 3'b001; //sub
                    RegEn <= 1'b0;
                end
                else begin
                    aluOut <= 3'b000; //Add
                    RegEn <= 1'b0;
                end
            4'b0111: begin 
                     aluOut <= 3'b111; //nor
                     RegEn <= 1'b0;
                     end
            4'b1110: 
                if(functBit == 1) begin
                    aluOut <= 3'b100; //and
                    RegEn <= 1'b0;
                end
                else begin
                    aluOut <= 3'b010; //or
                    RegEn <= 1'b0;
                end           
            4'b1111:
                if(functBit == 1) begin
                    aluOut <= 3'b110; //srl
                    RegEn <= 1'b0;
                end
                else begin
                    aluOut <= 3'b101; //sll
                    RegEn <= 1'b0;
                end
            4'b0110: begin
                     addi <= 1'b1; // addi
                     RegEn <= 1'b0;
                     end
            4'b1001: begin
                     FU <= 3'b010; // jump
                     RegEn <= 1'b1;
                     end
            4'b1100: begin
                     FU <= 3'b011; // branch
                     RegEn <= 1'b1;
                     end
            4'b1000: begin 
                     FU <= 3'b001; // jumpreg
                     RegEn <= 1'b1;
                     end
            4'b0001: begin
                     mem <= 1'b0; // load
                     RegEn <= 1'b0;
                     end
            4'b0010: begin
                     mem <= 1'b1; // store
                     RegEn <= 1'b1;
                     end
            default: aluOut <= 3'bxxxx; 
        endcase
        end
        endmodule