`timescale 1ns / 1ps

module CPU9bits(
    input wire reset, clk,
    output wire [8:0] result,
    output wire done
    );

    
    wire [8:0] RFIn,FUAddr;
    wire [1:0] instr;
    wire fetchBranch, RegEn;
    wire [50:0] FDOut, FDPipOut;
    wire [61:0] EMOut, EMPipOut;
    
    assign result = RFIn;
    
    FDModule FD(
        .reset(reset),
        .clk(clk),
        .FUIdx(fetchBranch),
        .En(RegEn),
        .RFIn(RFIn),
        .AddrIn(FUAddr), 
        .RFIdx(instr),
        .result(FDOut),
        .done(done)
     );
     
     fDPipReg pipe1(
        .clk(clk), 
	    .reset(reset), 
	    .En(RegEn), 
	    .Din(FDOut), 
	    .Dout(FDPipOut)
	 );
        
     EMModule EM(
        .reset(reset),
        .clk(clk),
        .PipIn(FDPipOut),
        .PipOut(EMOut)
     );
    
    eMPipReg pipe2(  
        .clk(clk), 
	    .reset(reset), 
	    .En(RegEn), 
	    .Din(EMOut), 
	    .Dout(EMPipOut)
	 );
    
     WMUdule W(
        .PipIn(EMPipOut),
        .RFIn(RFIn),
        .FUAddr(FUAddr),
        .instr(instr),
        .fetchBranch(fetchBranch), 
        .RegEn(RegEn)
     );

endmodule

module CPU9bits_tb();
    reg clk, reset;
    wire done;
    wire [8:0] result;

    initial begin
    	clk = 1'b0;
	end
	always begin
    	#5 clk = ~clk; // Period to be determined
	end


    CPU9bits CPU9bits0(
        .reset(reset),
        .clk(clk),
        .done(done),
        .result(result));
        
    initial begin
    	#5
    	reset = 1'b1;
    	#10
    	reset = 1'b0;
    	#50
        $finish;
        
    end
endmodule