Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Sat Feb 16 17:37:11 2019 | Host : DESKTOP-8QFGS52 running 64-bit major release (build 9200) | Command : report_clock_utilization -file FetchUnit_clock_utilization_routed.rpt | Design : FetchUnit | Device : 7k160ti-fbg484 | Speed File : -2L PRODUCTION 1.12 2017-02-17 | Temperature Grade : I -------------------------------------------------------------------------------------------- Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Clock Regions: Key Resource Utilization 5. Clock Regions : Global Clock Summary 6. Device Cell Placement Summary for Global Clock g0 7. Clock Region Cell Placement per Global Clock: Region X0Y1 1. Clock Primitive Utilization ------------------------------ +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ | BUFGCTRL | 1 | 32 | 0 | 0 | 0 | | BUFH | 0 | 120 | 0 | 0 | 0 | | BUFIO | 0 | 32 | 0 | 0 | 0 | | BUFMR | 0 | 16 | 0 | 0 | 0 | | BUFR | 0 | 32 | 0 | 0 | 0 | | MMCM | 0 | 8 | 0 | 0 | 0 | | PLL | 0 | 8 | 0 | 0 | 0 | +----------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 9 | 0 | | | clk_IBUF_BUFG_inst/O | clk_IBUF_BUFG | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+----------------------+---------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 3. Global Clock Source Details ------------------------------ +-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ | src0 | g0 | IBUF/O | None | IOB_X0Y78 | X0Y1 | 1 | 0 | | | clk_IBUF_inst/O | clk_IBUF | +-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+-----------------+----------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 4. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | | X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 9 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | | X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 | | X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 | | X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | | X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts 5. Clock Regions : Global Clock Summary --------------------------------------- All Modules +----+----+----+ | | X0 | X1 | +----+----+----+ | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 1 | 0 | | Y0 | 0 | 0 | +----+----+----+ 6. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ | g0 | BUFG/O | n/a | | | | 9 | 0 | 0 | 0 | clk_IBUF_BUFG | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+---------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+ | | X0 | X1 | +----+----+----+ | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 9 | 0 | | Y0 | 0 | 0 | +----+----+----+ 7. Clock Region Cell Placement per Global Clock: Region X0Y1 ------------------------------------------------------------ +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ | g0 | n/a | BUFG/O | None | 9 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | clk_IBUF_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+---------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y0 [get_cells clk_IBUF_BUFG_inst] # Location of IO Primitives which is load of clock spine # Location of clock ports set_property LOC IOB_X0Y78 [get_ports clk] # Clock net "clk_IBUF_BUFG" driven by instance "clk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" #startgroup create_pblock {CLKAG_clk_IBUF_BUFG} add_cells_to_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="clk_IBUF_BUFG"}]]] resize_pblock [get_pblocks {CLKAG_clk_IBUF_BUFG}] -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1} #endgroup