`timescale 1ns / 1ps

module ALU(
    input wire [2:0] opcode, // NOT the same as the instruction set opcode
    input wire [8:0] operand0,
    input wire [8:0] operand1,
    output wire [8:0] result 
    );
    
    // Wires for connecting the modules to the mux
    wire [8:0] result_A,result_B,result_C,result_D,result_E,result_F,result_G,result_H;
    
    // A (000) - Add
    add_9bit add0(
        .A(operand0),
        .B(operand1),
        .Cin(1'b0),
        .Sum(result_A));
    // B (001) - Subtract
    sub_9bit sub0(
        .A(operand0),
        .B(operand1),
        .C(result_B));
    // C (010) - OR
    or_9bit or0(
        .A(operand0),
        .B(operand1),
        .C(result_C));
    // D (011) - NOR
    nor_9bit nor0(
        .A(operand0),
        .B(operand1),
        .C(result_D));
    // E (100) - AND
    and_9bit and0(
        .A(operand0),
        .B(operand1),
        .C(result_E));
    // F (101) - Shift Logical Left
    shift_logical_left sll(
        .A(operand0),
        .B(result_F));
    // G (110) - Shift Logical Right
    shift_logical_right slr(
        .A(operand0),
        .B(result_G));
    // H (111)
    
    
    // MUX chooses which result to show based on the ALU's opcode
    mux_8_1 mux0(
        .switch(opcode),
        .A(result_A),
        .B(result_B),
        .C(result_C),
        .D(result_D),
        .E(result_E),
        .F(result_F),
        .G(result_G),
        .H(result_H),
        .out(result));

endmodule

//testbench
//module alu_tb();
//reg [8:0] a;
//reg [8:0] b;
//reg [2:0] c;
//wire [8:0] d;

//ALU alu0(
//.operand0(a),
//.operand1(b),
//.opcode(c),
//.result(d));
    
//    initial begin
//    a = 9'b000000111;
//    b = 9'b000111000;
//    c = 3'b000;
//    #5
//    a = 9'b000011000;
//    b = 9'b000011000;
//    c = 3'b001;
//    #5
//    a = 9'b101010100;
//    b = 9'b010101011;
//    c = 3'b010;
//    #5
//    a = 9'b101010100;
//    b = 9'b010101000;
//    c = 3'b011;
//    #5
//    a = 9'b000110000;
//    b = 9'b000111000;
//    c = 3'b100;
//    #5
//    a = 9'b01011000;
//    c = 3'b101;
//    #5
//    a = 9'b00001010;
//    c = 3'b110;
//    #5
//    #5 $finish;

//    end
//endmodule