`timescale 1ns / 1ps

module FetchUnit(input wire clk, reset, 
                 input wire [1:0] op_idx,
                 input wire [8:0] AddrIn,
                 output wire [8:0] AddrOut);
  
    //Wires from mux(result_m) to PC (progC_out) to adder then back to mux (result_a) 
    wire [8:0] progC_out, result_a, result_m;
    
    register PC(
        .clk(clk),
        .reset(reset),
        .En(2'b00),
        .Din(result_m),
        .Dout(progC_out));
    //Adds 1 to the program counter
    add_9bit PCAdder(
        .A(progC_out),
        .B(9'b000000001),
        .Cin(9'b000000000),
        .Sum(AddrOut));
        
    mux_2_1 PCmux(
        .A(AddrIn),
        .B(AddrOut),
        .out(result_m),
        .switch(op_idx));
        
        
endmodule

//testbench
//module fetchUnit_tb();
//reg [8:0] addr_in;
//reg opidx;
//reg reset;
//wire [8:0] addr_out;

//    reg clk;
//    initial begin
//        clk = 1'b0;
//    end
//    always begin
//        #5 clk = ~clk; // Period to be determined
//    end

//FetchUnit fetchUnit0(
//.clk(clk),
//.reset(reset),
//.op_idx(opidx),
//.AddrIn(addr_in),
//.AddrOut(addr_out));


    
//    initial begin
//    reset = 0;
//    opidx = 1'b1;
//    addr_in = 0'b000000000;
//    #5
//    reset = 1;
//    #5
//    reset = 0;
//    opidx = 1'b0;
//    addr_in = 9'b000001111;
//    #5
//    #5
//    addr_in = 9'b011000011;
//    #5
//    #5
//    opidx = 1'b1;
//    #5
//    #5
//    #5
//    #5
//    opidx = 1'b0;
//    addr_in = 9'b000001111;
//    #5
//    #5
//    addr_in = 9'b010010011;
//    #5
//    opidx = 1'b1;
//    #5
//    #5
//    #5
//    #5
//    #5 $finish;

//    end
//endmodule