`timescale 1ns / 1ps

module dataMemory(
    input wire clk, writeEnable,
    input wire [8:0] address, writeData,
    output reg [8:0] readData
    );
    
    reg [8:0] memory [15:0];
    
    initial begin
//        // String Compare Memory
//        memory[0] <= 9'b000000100;
//        memory[1] <= 9'b000001000;
//        memory[2] <= 9'b000001100;
//        memory[3] <= 9'b010101010;
//        memory[4] <= 9'b000001111;
//        memory[5] <= 9'b000000100;
//        memory[6] <= 9'b000000011;
//        memory[7] <= 9'b000000000;
//        memory[8] <= 9'b000001111;
//        memory[9] <= 9'b000000100;
//        memory[10] <= 9'b000000010;
//        memory[11] <= 9'b000000000;
//        memory[12] <= 9'b000000000;
//        memory[13] <= 9'b000000000;
//        memory[14] <= 9'b000000000;
//        memory[15] <= 9'b000000000;

        // Bubble Sort Initial Memory
        
           memory[0] <= 9'b000011000;
           memory[1] <= 9'b000000000;
           memory[2] <= 9'b000100000;
           memory[3] <= 9'b010001000;
           memory[4] <= 9'b010010000;
           memory[5] <= 9'b010011000;
           memory[6] <= 9'b101001000;
           memory[7] <= 9'b101001010;
           memory[8] <= 9'b000100011;
           memory[9] <= 9'b101001001;
          memory[10] <= 9'b011001001;
          memory[11] <= 9'b001001000;
          memory[12] <= 9'b101001001;
          memory[13] <= 9'b011101000;
          memory[14] <= 9'b110001010;
          memory[15] <= 9'b000100001;
          memory[16] <= 9'b100110100;
          memory[17] <= 9'b000001001;
          memory[18] <= 9'b011001001;
          memory[19] <= 9'b000110010;
          memory[20] <= 9'b000000001;
          memory[21] <= 9'b000111010;
          memory[22] <= 9'b101011110;
          memory[23] <= 9'b011111100;

        // Binary Search Memory
//         memory[0] <= 9'b000000000;
//         memory[1] <= 9'b000000111;
//         memory[2] <= 9'b000000001;
//         memory[3] <= 9'b000000010;
//         memory[4] <= 9'b000000011;
//         memory[5] <= 9'b000000100;
//         memory[6] <= 9'b000000101;
//         memory[7] <= 9'b000000110;
//         memory[8] <= 9'b000000111;
//         memory[9] <= 9'b000001000;
//        memory[10] <= 9'b000001001;
//        memory[11] <= 9'b000001010;
//        memory[12] <= 9'b000001011;
//        memory[13] <= 9'b000001100;
//        memory[14] <= 9'b000001101;
//        memory[15] <= 9'b000001110;
//        memory[16] <= 9'b000001111;
//        memory[17] <= 9'b000010000;
//        memory[18] <= 9'b000010001;
//        memory[19] <= 9'b000010010;
        
    end

    always@(address, clk, memory)begin
        if(clk == 1'b1)begin
        readData <= memory[address];
        if(writeEnable == 1'b1)begin
        memory[address] <= writeData;
        end
        else begin
        memory[address] <= memory[address];
        end
        end
    end      
endmodule

module dataMemory_tb();
    reg clk, writeEnable;
    reg [8:0] address, writeData;
    wire [8:0] readData;
    
        initial begin
        clk = 1'b0;
    end
    always begin
        #5 clk = ~clk; // Period to be determined
    end
    
    dataMemory dM0(
        .clk(clk),
        .writeEnable(writeEnable),
        .writeData(writeData),
        .address(address),
        .readData(readData)
    );
    
    initial begin
        writeEnable = 1'b0;
        address = 9'b000000000;
        writeData = 9'b010101010;
        #5
        address = 9'b000000100;
        writeData = 9'b010101010;
        #10
        writeEnable = 1'b1;
        address = 9'b000000000;
        writeData = 9'b010101010;
        #10
        address = 9'b000000001;
        writeData = 9'b000001111;
        #10
        address = 9'b000000010;
        writeData = 9'b000000101;
        #10
        address = 9'b000000011;
        writeData = 9'b000000011;
        #10
        address = 9'b00000010;
        writeData = 9'b000001101;
        #5
        $finish;
    end
endmodule