`timescale 1ns / 1ps

module ControlUnit(
    input wire [3:0] instIn,
    input wire functBit,
    output reg [3:0] aluOut,
    output reg [2:0] FU,
    output reg addi,
    output reg mem,
    output reg load,
    output reg RegEn);
    
        always @(instIn)begin
            case(instIn)
            4'b0101:
                if(functBit == 1) begin
                    aluOut <= 4'b0001; //sub
                    RegEn <= 1'b0;
                end
                else begin
                    aluOut <= 4'b0000; //Add
                    RegEn <= 1'b0;
                end
            4'b1101: begin 
                     aluOut <= 4'b0011; //nor
                     RegEn <= 1'b0;
                     end
            4'b1110: 
                if(functBit == 1) begin
                    aluOut <= 4'b0100; //and
                    RegEn <= 1'b0;
                end
                else begin
                    aluOut <= 4'b0010; //or
                    RegEn <= 1'b0;
                end           
            4'b1111:
                if(functBit == 1) begin
                    aluOut <= 4'b0110; //srl
                    RegEn <= 1'b0;
                end
                else begin
                    aluOut <= 4'b0101; //shift left
                    RegEn <= 1'b0;
                end
            4'b0111: begin 
                     aluOut <= 4'b1001; //Less than
                     RegEn <= 1'b0;
                end
            4'b0110: begin
                     addi <= 1'b1; // addi
                     RegEn <= 1'b0;
                end
            4'b1001: begin
                     FU <= 3'b010; // jump
                     RegEn <= 1'b1;
                end
            4'b1100: begin
                     FU <= 3'b011; // branch
                     RegEn <= 1'b1;
                end
            4'b1000: begin 
                     FU <= 3'b001; // jumpreg
                     RegEn <= 1'b1;
                end
            4'b0001: begin
                     mem <= 1'b0; // load
                     RegEn <= 1'b0;
                end
            4'b0010: begin
                     mem <= 1'b1; // store
                     RegEn <= 1'b1;
                end
            default: aluOut <= 4'bxxxx; 
        endcase
    end
endmodule
        
        
module ControlUnit_tb();
    reg [3:0] instruction;
    reg functionB;
    wire [3:0] aluOutput;
    wire [2:0] FetchUnit;
    wire addImmediate;
    wire memory;
    wire loadIt;
    wire RegEnable;
    

    ControlUnit ControlUnit0(
        .instIn(instruction),
        .functBit(functionB),
        .aluOut(aluOutput),
        .FU(FetchUnit),
        .addi(addImmediate),
        .mem(memory),
        .load(loadIt),
        .RegEn(RegEnable)
        );
    
    initial begin
        functionB = 1'b0;
        instruction = 4'b0101;
        #5
        functionB = 1'b1;
        #5
        functionB = 1'b0;
        instruction = 4'b1110;
        #5
        functionB = 1'b1;
        #5
        functionB = 1'b0;
        instruction = 4'b1111;
        #5
        functionB = 1'b1;
        #5
        instruction = 4'b0111;
        #5
        instruction = 4'b0110;
        #5
        instruction = 4'b1001;
        #5
        instruction = 4'b1100;
        #5
        instruction = 4'b1000;
        #5
        instruction = 4'b0001;
        #5
        instruction = 4'b0010;
        #5
        $finish;

    end
endmodule