`timescale 1ns / 1ps

module CPU9bits(
    input wire reset, clk,
    output reg [8:0] result,
    output wire done
    );

    wire [8:0] instr, op1, op0, FUAddr,FUJB,PCout,JBRes,FUJ,FUB,AddiOut,AluOut,RFIn, loadMux, dataMemOut, linkData, SE1N, SE2N, SE3N, bankData, bankOP,jumpNeg;
    wire [3:0] aluOp;
    wire [2:0] FU;
    wire [1:0] bankS;
    wire addiS, RegEn, loadS, fetchBranch, halt, cout0, cout1, link, js, dataMemEn;

    instructionMemory iM(
        .address(PCout),
        .readData(instr)
    );

    dataMemory dM(
        .clk(clk),
        .writeEnable(dataMemEn),
        .writeData(op0),
        .address(op1),
        .readData(dataMemOut)
    );    

    RegFile RF(
        .clk(clk),
        .reset(reset),
        .enable(RegEn),
        .write_index(instr[4:3]),
        .op0_idx(instr[4:3]),
        .op1_idx(instr[2:1]),
        .write_data(RFIn),
        .op0(op0),
        .op1(op1)
    );

    RegFile Bank(
        .clk(clk),
        .reset(reset),
        .enable(bankS[1]),
        .write_index(instr[2:1]),
        .op0_idx(instr[2:1]),
        .op1_idx(2'b00),//Doesn't matter
        .write_data(op0),
        .op0(bankOP),
        .op1()
    );

    FetchUnit FetchU(
        .clk(clk),
        .reset(reset),
        .op_idx(fetchBranch),
        .AddrIn(FUAddr),
        .AddrOut(PCout)
    );

    ALU alu(
        .opcode(aluOp),
        .operand0(op0),
        .operand1(op1),
        .result(AluOut)     
    );

    ControlUnit CU(
        .instIn(instr[8:5]),
        .functBit(instr[0]),
        .aluOut(aluOp),
        .FU(FU),
        .addi(addiS),
        .mem(loadS),
        .dataMemEn(dataMemEn),
        .RegEn(RegEn),
        .halt(done),
        .link(link),
        .bank(bankS),
        .js(js)
    );


     //-----------------------Fetch Unit Stuff

    add_9bit JBAdder(
        .A(PCout),
        .B(JBRes),
        .Cin(1'b0),
        .Sum(FUJB),
        .Cout(cout0)
    );

    mux_2_1 mux0(
        .A(op0),
        .B(FUJB),
        .out(FUAddr),
        .switch(FU[1])
    );

    twos_compliment_9bit two_comp0(
        .A({4'b0000,instr[4:0]}),
        .B(jumpNeg)
    );

    mux_2_1 mux1(
        .A({4'b0000,instr[4:0]}),
        .B(jumpNeg),
        .out(SE2N),
        .switch(js)
    );

    mux_2_1 mux2(
        .A(SE2N), //Jump -- Change with signer module!
        .B(SE1N),//Branch -- Change with signer module!
        .out(JBRes),
        .switch(FU[2])
    );

    sign_extend_3bit SE1(
        .A(instr[2:0]),
        .B(SE1N)
    );

    bit1_mux_2_1 BranMux( // BEQ MUX
        .A(FU[0]),
        .B(AluOut[0]),
        .out(fetchBranch),
        .switch(FU[2]) // FU[2] only goes high when BEQ
    );

    ///--------------------------Addi Stuff

    add_9bit Addier(
        .A(SE3N), // Change with signer module!
        .B(op0),
        .Cin(1'b0),
        .Sum(AddiOut),
        .Cout(cout1)
    );

    sign_extend_3bit SE3(
        .A(instr[2:0]),
        .B(SE3N)
    );

    mux_2_1 mux3(
        .A(AluOut),
        .B(AddiOut),
        .out(loadMux),
        .switch(addiS)
    );

    ///--------------------------Mem stuff

    mux_2_1 mux4(
        .A(linkData),
        .B(dataMemOut), // This is DATA MEM
        .out(bankData),
        .switch(loadS)
    );

    ///--------------------------Bank stuff

    mux_2_1 mux5(
        .A(bankData),
        .B(bankOP), 
        .out(RFIn),
        .switch(bankS[0])
    );

    ///--------------------------Link Stuff

    mux_2_1 mux6(
        .A(loadMux),
        .B(PCout),
        .out(linkData),
        .switch(link)
    );

    always @ (instr, dataMemOut, AluOut, AddiOut)
    begin
        case(instr[8:5])
        4'b0001: // Load Byte
            result <= dataMemOut;
        4'b0101: // Add/Subtract
            result <= AluOut;
        4'b0110: // Add Immediate
            result <= AddiOut;
        4'b0111: // Set if Less Than
            result <= AluOut;
        4'b1101: // NOR
            result <= AluOut;
        4'b1110: // OR/AND
            result <= AluOut;
        4'b1111: // Shift Right Logical/Shift Left Logical
            result <= AluOut;
        default:
            result <= 9'bXXXXXXXXX;
        endcase
    end

endmodule

module CPU9bits_tb();
    reg clk, reset;
    wire done;

    always
        #5 clk = ~clk; // Period to be determined

    CPU9bits CPU9bits0(
        .reset(reset),
        .clk(clk),
        .done(done),
        .result()
        );
        
    initial begin
        clk = 1'b0;
        reset = 1'b1;
        #5
        reset = 1'b0;
        #5
        reset = 1'b1;
    
//        instruction = 9'b000100000;
//        reset = 1'b1;
//        #10
//        reset = 1'b0;
//        #10
//        instruction = 9'b000101000;
//        #10
//        instruction = 9'b010100010;
//        #10
//        instruction = 9'b111100000;
//        #10
//        instruction = 9'b111100000;
//        #10
//        instruction = 9'b001101000;
//        #10
//        instruction = 9'b010001000;
//        #10
//        instruction = 9'b000000000;
//        #10    
        $finish;
        
    end
endmodule