#----------------------------------------------------------- # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # Start of session at: Fri Feb 15 12:30:55 2019 # Process ID: 11860 # Current directory: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1 # Command line: vivado.exe -log RegFile.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source RegFile.tcl -notrace # Log file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile.vdi # Journal file: C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1\vivado.jou #----------------------------------------------------------- source RegFile.tcl -notrace Command: link_design -top RegFile -part xc7k160tifbg484-2L Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Project 1-479] Netlist was created with Vivado 2018.3 INFO: [Device 21-403] Loading part xc7k160tifbg484-2L INFO: [Project 1-570] Preparing netlist for logic optimization Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 583.539 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 589.113 ; gain = 334.250 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 603.453 ; gain = 14.340 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: aad14af3 Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1128.941 ; gain = 525.488 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: aad14af3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 1225.754 ; gain = 0.000 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: aad14af3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.060 . Memory (MB): peak = 1225.754 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep Phase 3 Sweep | Checksum: aad14af3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.067 . Memory (MB): peak = 1225.754 ; gain = 0.000 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 4 BUFG optimization Phase 4 BUFG optimization | Checksum: aad14af3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.071 . Memory (MB): peak = 1225.754 ; gain = 0.000 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization Phase 5 Shift Register Optimization | Checksum: aad14af3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.124 . Memory (MB): peak = 1225.754 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: aad14af3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.126 . Memory (MB): peak = 1225.754 ; gain = 0.000 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 0 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 0 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000 Ending Logic Optimization Task | Checksum: aad14af3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.129 . Memory (MB): peak = 1225.754 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: aad14af3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1225.754 ; gain = 0.000 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: aad14af3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000 Ending Netlist Obfuscation Task | Checksum: aad14af3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 20 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1225.754 ; gain = 636.641 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1225.754 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file RegFile_drc_opted.rpt -pb RegFile_drc_opted.pb -rpx RegFile_drc_opted.rpx Command: report_drc -file RegFile_drc_opted.rpt -pb RegFile_drc_opted.pb -rpx RegFile_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.3/data/ip'. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_drc_opted.rpt. report_drc completed successfully Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7fa8ebe0 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1225.754 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1225.754 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: ae3aece4 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 182815a23 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 182815a23 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121 Phase 1 Placer Initialization | Checksum: 182815a23 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121 Phase 2 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1238.875 ; gain = 0.000 Phase 2 Final Placement Cleanup | Checksum: 182815a23 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121 INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed Ending Placer Task | Checksum: ae3aece4 Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1238.875 ; gain = 13.121 INFO: [Common 17-83] Releasing license: Implementation 38 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1238.875 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.151 . Memory (MB): peak = 1238.875 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file RegFile_io_placed.rpt report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.112 . Memory (MB): peak = 1243.988 ; gain = 5.113 INFO: [runtcl-4] Executing : report_utilization -file RegFile_utilization_placed.rpt -pb RegFile_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file RegFile_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1243.988 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160ti' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160ti' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Checksum: PlaceDB: 2e920104 ConstDB: 0 ShapeSum: 7fa8ebe0 RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: ccf0732b Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1467.336 ; gain = 220.660 Post Restoration Checksum: NetGraph: 2e7f4797 NumContArr: 9e712b94 Constraints: 0 Timing: 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: ccf0732b Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1471.402 ; gain = 224.727 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: ccf0732b Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1471.402 ; gain = 224.727 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: b146062c Time (s): cpu = 00:00:41 ; elapsed = 00:00:31 . Memory (MB): peak = 1478.180 ; gain = 231.504 Phase 3 Initial Routing Number of Nodes with overlaps = 0 Phase 3 Initial Routing | Checksum: b146062c Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Phase 4.1 Global Iteration 0 | Checksum: b146062c Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930 Phase 4 Rip-up And Reroute | Checksum: b146062c Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930 Phase 5 Delay and Skew Optimization Phase 5 Delay and Skew Optimization | Checksum: b146062c Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1 Hold Fix Iter | Checksum: b146062c Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930 Phase 6 Post Hold Fix | Checksum: b146062c Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0 % Global Horizontal Routing Utilization = 0 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 0%, No Congested Regions. South Dir 1x1 Area, Max Cong = 0%, No Congested Regions. East Dir 1x1 Area, Max Cong = 0%, No Congested Regions. West Dir 1x1 Area, Max Cong = 0%, No Congested Regions. ------------------------------ Reporting congestion hotspots ------------------------------ Direction: North ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: South ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Phase 7 Route finalize | Checksum: b146062c Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1482.605 ; gain = 235.930 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: b146062c Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1484.613 ; gain = 237.938 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: b146062c Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1484.613 ; gain = 237.938 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:00:42 ; elapsed = 00:00:32 . Memory (MB): peak = 1484.613 ; gain = 237.938 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 50 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:33 . Memory (MB): peak = 1484.613 ; gain = 240.625 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1484.613 ; gain = 0.000 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.058 . Memory (MB): peak = 1484.613 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file RegFile_drc_routed.rpt -pb RegFile_drc_routed.pb -rpx RegFile_drc_routed.rpx Command: report_drc -file RegFile_drc_routed.rpt -pb RegFile_drc_routed.pb -rpx RegFile_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_drc_routed.rpt. report_drc completed successfully INFO: [runtcl-4] Executing : report_methodology -file RegFile_methodology_drc_routed.rpt -pb RegFile_methodology_drc_routed.pb -rpx RegFile_methodology_drc_routed.rpx Command: report_methodology -file RegFile_methodology_drc_routed.rpt -pb RegFile_methodology_drc_routed.pb -rpx RegFile_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file C:/Users/JoseIgnacio/CA Lab/lab2CA.runs/impl_1/RegFile_methodology_drc_routed.rpt. report_methodology completed successfully INFO: [runtcl-4] Executing : report_power -file RegFile_power_routed.rpt -pb RegFile_power_summary_routed.pb -rpx RegFile_power_routed.rpx Command: report_power -file RegFile_power_routed.rpt -pb RegFile_power_summary_routed.pb -rpx RegFile_power_routed.rpx WARNING: [Power 33-232] No user defined clocks were found in the design! Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation 61 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file RegFile_route_status.rpt -pb RegFile_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file RegFile_timing_summary_routed.rpt -pb RegFile_timing_summary_routed.pb -rpx RegFile_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. INFO: [runtcl-4] Executing : report_incremental_reuse -file RegFile_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file RegFile_clock_utilization_routed.rpt INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file RegFile_bus_skew_routed.rpt -pb RegFile_bus_skew_routed.pb -rpx RegFile_bus_skew_routed.rpx INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2L, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs INFO: [Common 17-206] Exiting Vivado at Fri Feb 15 12:32:12 2019...